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61 commits

Author SHA1 Message Date
zmt00
7e66e082fd tests/A64: Add SABD tests 2024-01-23 18:28:19 +00:00
zmt00
77f1f0376f tests/A64: Add {U,S}MINP.H, {U,S}MAXP.H tests 2024-01-10 12:23:28 +00:00
zmt00
bd841cfd3e tests/A64: Add {U,S}MINP.S, {U,S}MAXP.S tests 2024-01-02 19:04:02 +00:00
zmt00
521bf64ef2 tests/A64: Add remaining UZP unit tests. 
Additionally changed the numeric values of the test vectors in the
32-bit element tests to match the pattern of the other tests - this
makes it easier to tell at a glance what elements are out of place if a
test fails.
 2023-12-17 21:56:55 +00:00
zmt00
7ef11ee311 tests/A64: Add VUZP{1,2}.H unit tests 2023-12-11 13:18:19 +00:00
zmt00
d68b916f57 tests/A64: Add VUZP{1,2}.S unit tests 2023-12-02 20:33:45 +00:00
Merry
0fd9d781b5 tests: Ensure issue #727 resolved 2023-01-15 03:01:49 +00:00
Merry
2d1edf1c80 emit_x64_floating_point: Fix register allocation bug in FPTwoOp 
Erroneous use of ScratchXmm in conditional path
 2023-01-15 02:29:08 +00:00
Merry
31a684361f tests: Update to Catch2 v3 2022-12-31 17:28:34 +00:00
Merry
0869c26b4f tests/fp_min_max: Add a few more test cases 2022-12-29 19:09:06 +00:00
Merry
c804b3980d tests: Add FMAX/FMIN/FMAXNM/FMINNM tests 2022-12-29 19:08:45 +00:00
Liam
21b4211414 Add test for isolated GetNZCVFromOp 2022-12-03 11:16:26 -05:00
Liam
16101049f3 Fix EXTR (flipped rgister order) 2022-12-03 11:16:26 -05:00
Merry
038b728797 emit_x64_data_processing: Detect overflow on division 2022-11-29 14:15:12 +00:00
Merry
6bcc424e1a emit_x64_vector: Ensure FPSR.QC is set even if output is invalidated 2022-07-20 19:44:39 +01:00
Wunkolo
f0b9cb9ccf tests/A64: Add {S,U}SHL instruction unit tests 2022-04-06 17:41:55 +01:00
Wunkolo
69b831d7d2 tests: Add {S,V}ADD{V,P} tests 
These are the instructions emitted for each variant of the `vaddv{q}_{s}{8,16,32,64}` intrinsic.
 2021-09-27 19:54:11 +01:00
Merry
2bc86209bd catch: Correct include directory 2021-08-08 12:52:55 +01:00
Wunkolo
f171ce7859 tests: Add FMLA(lane) test 
Math operations such as Matrix multiplication utilize these particular
instructions enough that there should be some unit tests for thesein particular.
The lane-splatting form of FMUL and FMLA instructions are of particular
interest and I've found them to be very common in retail game binaries
such as Pokemon Sword.

https://community.arm.com/developer/ip-products/processors/b/processors-ip-blog/posts/coding-for-neon---part-3-matrix-multiplication

I'm primarily adding this unit test so that I can ensure compatibility
while I tune and optimize them.
 2021-08-07 23:03:57 +01:00
Wunkolo
a1192a51d8 tests: add F{MIN,MAX}NM tests 2021-06-20 10:12:27 +01:00
Wunkolo
759459e181 tests: Add FABS tests 2021-06-10 00:04:57 +01:00
Wunkolo
87aac2a46b tests: Add F{MIN,MAX} tests 
Very minimal tests that includes some denormals and {Q,S}NANs
 2021-06-08 17:50:28 +01:00
Markus Wick
0c12614d1a A64/config.h: Split fastmem and page_table options. 
We might want to allocate different sizes for each of them.
e.g. for the unsafe fastmem approach without bounds checking.
Or for using the full 48bit adress range (with mirrors) by allocating our real arena as close to 1<<47 as possible.
 2021-06-06 17:25:51 +01:00
MerryMage
0a77ee1a58 tests: Format to clang-format mandated style 2021-05-31 12:54:27 +01:00
Jeremy Van de woestyne
b4ee976a6f unit tests & various fixes 2021-05-28 18:49:31 +01:00
Wunkolo
e8c266d0d3 tests/A64: Add VQADD/VQSUB unit tests 2021-05-28 14:13:11 +01:00
Wunkolo
3c693f2576 emit_x64_vector: AVX512VBMI implementation of EmitVectorTableLookup128 
Also adds AVX512VBMI detection to host_feature
 2021-05-22 22:48:31 +01:00
Wunkolo
9ba5e8e52d tests/A64: Add TBL/TBX instruction unit tests 
Tests the TBL instruction with implementation with {1-4} register
lookups and the handling of out-of-bound indices.
Intended to target the implementation of VectorTableLookup128
 2021-05-22 22:47:21 +01:00
MerryMage
53493b2024 Add .clang-format file 
Using clang-format version 12.0.0
 2021-05-22 15:07:02 +01:00
Merry
714216fd0e Consolidate all source files into src/ directory 2021-05-19 17:41:59 +01:00
Wunkolo
2c0be5e18c emit_x64_vector: AVX512 Implementation of EmitVectorNarrow{32,64} 
Includes a new test case with the XTN instruction to verify
the implementation
 2021-05-16 10:02:49 +01:00
emuplz
6d4333c78e fixed data + instruction cache callbacks (w/ tests) 2021-02-17 20:38:08 +00:00
rufi
77621a8448 implemented other ic instructions 2021-02-17 20:38:08 +00:00
emuplz
8728444af8 added support for instruction ic ivau 2021-02-17 20:38:06 +00:00
MerryMage
4ba1f8b9e7 Add optimization flags to disable specific optimizations 2020-07-04 11:04:10 +01:00
MerryMage
9f3277540a Merge A32 and A64 exclusive monitors 2020-06-17 10:33:09 +01:00
Fernando Sahmkow
97b9d3e058 Exclusive Monitor: Rework exclusive monitor interface. 2020-05-03 01:40:37 +01:00
MerryMage
24229ab899 constant_propagation_pass: Don't fold add if we nee flags 
Results in incorrect flags
 2020-04-29 15:33:12 +01:00
MerryMage
0d041696f5 tests/a64: Reminder about hidden infinite loops 2020-04-23 18:11:45 +01:00
MerryMage
a8a712c801 Relicense to 0BSD 2020-04-23 15:45:57 +01:00
MerryMage
06b31448aa emit_x64_vector: Changes to VectorSignedSaturatedDoublingMultiply 
* Return both the upper and lower parts of the multiply if required
* SSE2 does not support the pmuldq instruction, do sign correction to an unsigned result instead
* Improve port utilisation where possible (punpck instructions were a bottleneck)
 2020-04-22 20:55:06 +01:00
MerryMage
3caeb62ef1 emit_x64_floating_point: Hardware FMA implementation of FPRSqrtStepFused 2020-04-22 20:55:06 +01:00
MerryMage
b8daa4feac simd_two_register_misc: FNEG (vector) with Q == 0 had dirty upper 2020-04-22 20:55:05 +01:00
MerryMage
656ceff225 emit_x64_floating_point: Fix smallest normal check in EmitFPMulAdd 2020-04-22 20:53:45 +01:00
MerryMage
35c758f211 tests: Refactor unicorn_emu to allow for A32 unicorn 2020-04-22 20:46:23 +01:00
MerryMage
ff84740ea6 testenv: Make code_mem mobile 2020-04-22 20:46:23 +01:00
MerryMage
bb93353f94 emit_x64_vector_floating_point: Correct FMA in FTZ mode 
x64 rounds before flushing to zero
AArch64 rounds after flushing to zero

This difference of behaviour is noticable if something would round to a smallest normalized number
 2020-04-22 20:46:23 +01:00
MerryMage
822fd4a875 backend_x64: Fix FPVectorMulAdd and FPMulAdd NaN handling with denormals 
Denormals should be treated as zero in NaN handler
 2020-04-22 20:46:23 +01:00
MerryMage
76b07d6646 u128: StickyLogicalShiftRight requires special-casing for amount == 64 
In this case (128 - amount) == 64, and this invokes undefined behaviour
 2020-04-22 20:46:21 +01:00
MerryMage
0ce11b7b15 emit_x64_floating_point: Implement accurate fallback for FPMulAdd{32,64} 2020-04-22 20:46:21 +01:00