MerryMage
83022322d1
Make IR->A32 LocationDescriptor conversion explicit
2020-04-22 20:39:27 +01:00
MerryMage
9d15e0a8e1
Final A32 refactor
2020-04-22 20:39:27 +01:00
MerryMage
455757d7b6
EmitX64: JitState type as template parameter
2020-04-22 20:39:26 +01:00
MerryMage
2d164d9345
Package up emit context
2020-04-22 20:38:31 +01:00
MerryMage
7bf421dd38
Rename JitState to A32JitState
2020-04-22 20:38:31 +01:00
MerryMage
63bd1ece23
backend_x64: Split A32 specific emission into separate class
2020-04-22 20:38:29 +01:00
MerryMage
8bef20c24d
IR: Split off A32 specific opcodes
2020-04-22 20:33:32 +01:00
MerryMage
b1f0cf9278
A32: Split off A32 specific IREmitter
2020-04-22 20:33:32 +01:00
MerryMage
b3c73e2622
Label A32 specific code appropriately
2020-04-22 20:33:30 +01:00
MerryMage
dc357c780d
EmitPackedHalvingSub{U,S}16: SSE2 implementation
2020-04-22 20:27:15 +01:00
MerryMage
a98821da41
Merge branch 'misc'
...
These commits introduce context save and restore, and a small number of
optimizations that depend on their use for performance.
2020-04-22 20:27:15 +01:00
MerryMage
fc885ac80f
EmitPackedHalvingAddU8: Add SSE2 implementation
2020-04-22 20:27:15 +01:00
MerryMage
4682211729
EmitPackedHalvingAdd{U,S}16: Add SSE2 implementation
2020-04-22 20:27:15 +01:00
MerryMage
9ac1c87a51
emit_x64: EmitSet{Register,ExtendedRegister32,ExtendedRegister64}: Store from current source
2020-04-22 20:27:15 +01:00
MerryMage
6e834de072
Add re-entry prediction to avoid std::unordered_map lookups
2020-04-22 20:26:40 +01:00
MerryMage
984ce22431
emit_x64: Arguments to MostSignificantBit and IsZero are 32-bit
2020-04-22 20:26:40 +01:00
MerryMage
5c6fcf378f
emit_x64: Optimize code emitted by EmitGetCpsr
2020-04-22 20:26:40 +01:00
MerryMage
f595f85039
block_of_code: Remove vzeroupper
2020-04-22 20:26:40 +01:00
MerryMage
4393473d06
interface: Allow saving and storing of contexts
2020-04-22 20:26:40 +01:00
MerryMage
05f3f07704
emit_x64: Reduce mxscr operations in EmitGetFpscr and EmitSetFpscr
2020-04-22 20:26:40 +01:00
MerryMage
19a7fb8992
jit_state: Split off CPSR.NZCV
2020-04-22 20:26:40 +01:00
MerryMage
a3432102b8
jit_state: Split off CPSR.Q
2020-04-22 20:26:40 +01:00
MerryMage
4f8675083c
interface_x64: Fix MSVC cast warning
2020-04-22 20:26:40 +01:00
MerryMage
311361b409
jit_state: Split off CPSR.{E,T}
...
This allows us to improve code-emission for PopRSBHint. We also improve
code emission other terminals at the same time.
2020-04-22 20:26:40 +01:00
MerryMage
cb119c2f72
emit_x64: Use boost::icl::interval_map to speed up ranged invalidation
2020-04-22 20:26:40 +01:00
MerryMage
3cca3bbd0b
jit_state: Split off CPSR.GE
2020-04-22 20:26:40 +01:00
MerryMage
6fde29f5d8
emit_x64: Remove unnecessary ABI overhead in ReadMemory, WriteMemory
2020-04-22 20:26:40 +01:00
MerryMage
6adc554b53
jit_state: Hide cpsr implementation
2020-04-22 20:26:40 +01:00
MerryMage
eb80aae9c0
block_of_code: Move MXCSR switching out of dispatch loop
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Also clarify MXCSR entry/exit terminology
2020-04-22 20:26:40 +01:00
MerryMage
a4e85ad565
emit_x64: Make RSB a stack
2020-04-22 20:26:40 +01:00
MerryMage
2a818f9d8e
Merge branch 'timing'
...
We do this to improve timing information before entering a supervior
function. We also do this to try and stay within JITted code as much
as possible, by updating the cycles we have remaining.
2020-04-22 20:26:37 +01:00
MerryMage
ea4c3292d5
BlockOfCode: Detect space remaining
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We also clear the code cache when we run out of space.
This closes #111 .
2020-04-22 20:26:12 +01:00
MerryMage
256749910f
Add AddTicks and GetTicksRemaining callbacks
2020-04-22 20:26:12 +01:00
MerryMage
80c56aa89d
Remove unnecessary use of boost::make_optional
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Closes #119 .
2020-04-22 20:26:12 +01:00
MerryMage
639f7cfd2d
reg_alloc: Add IsLastUse optimization for UseScratch
2020-04-22 20:26:12 +01:00
MerryMage
6b122751fe
reg_alloc: Remove reliance on IR::Inst::DecrementRemainingUses
2020-04-22 20:26:12 +01:00
MerryMage
30049ca928
emit_x86: Standardize time of DefineValue call
2020-04-22 20:26:12 +01:00
MerryMage
12eaf496fd
emit_x64: Perform mask creation for packed instructions in SSE
2020-04-22 20:26:07 +01:00
MerryMage
305e4baa29
emit_x64: Eliminate conversion of GE flags
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* We do this so that we can simplify PackedSelect.
* We also try to minimise xmm-gpr/gpr-xmm transfers in PackedSelect.
2020-04-22 20:26:07 +01:00
MerryMage
d1e0a29cd9
Implement IR instruction PackedSelect, reimplement SEL
2020-04-22 20:26:07 +01:00
MerryMage
18f11972c6
emit_x64: Remove SSSE3 implementation of PackedHalvingAddU8
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It is much slower than the SSE2 implementation, so there's no point keeping it around.
2020-04-22 20:26:07 +01:00
MerryMage
c4b40909f7
emit_x64: Improve code emission of FPCompare{32,64}
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Replace if-chain with table lookup
2020-04-22 20:26:07 +01:00
MerryMage
814e378249
VCMP and VCMPE were the other way around
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- This was due to a misunderstanding of what the E in VCMPE means.
- The E refers to an exception being raised when a QNaN is encountered.
- Added unit tests for VCMP{E}
2020-04-22 20:26:07 +01:00
MerryMage
08f638d447
emit_x64: pmaxuw and pminuw require SSE 4.1
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This commit is intended to close citra-emu/citra#3137 .
pmaxuw and pminuw were used to perform unsigned comparisons; we emulate
these using a signed comparison by offsetting the inputs by 0x8000 for
CPUs that do not support SSE 4.1.
2020-04-22 20:26:07 +01:00
Mat M
77fe2aeeaa
emit_x64: Amend doxygen parameters for InvalidateCacheRange() ( #116 )
2020-04-22 20:22:01 +01:00
MerryMage
19dcdde90b
block_of_code: Add vzeroupper instructions where AVX-SSE transitions may occur
2020-04-22 20:22:01 +01:00
MerryMage
60d9392b5c
block_of_code: BlockOfCode should provide cpu info
2020-04-22 20:22:01 +01:00
MerryMage
148c01e08f
interface_x64: Remove is_executing assert from HaltExecution
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In multithreaded code this can be triggered due to a race.
2017-10-14 23:35:01 +01:00
MerryMage
f6cf265bc5
block_of_code: BlockOfCode::ABI_* should be const
2017-09-29 01:35:24 +01:00
MerryMage
29471be317
Standardize location of storage-class specifiers: Place at beginning of declarations
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Justification: C99 specifies that doing otherwise is an obsolescent feature.
2017-09-29 01:23:45 +01:00