dynarmic

Author	SHA1	Message	Date
MerryMage	5eb0bdecdf	IR: Simplify types. F32 -> U32, F64 -> U64, F128 -> U128 ARM's Architecture Specification Language doesn't distinguish between floats and integers as much as we do. This makes some things difficult to implement. Since our register allocator is now capable of allocating values to XMMs and GPRs as necessary, the Transfer IR instructions are no longer necessary as they used to be and they can be removed.	2020-04-22 20:42:46 +01:00
MerryMage	6395f09f94	IR: Implement Conditional Select	2020-04-22 20:42:45 +01:00
MerryMage	c09e69bb97	A64: Implement addsub instructions	2020-04-22 20:42:44 +01:00
MerryMage	d1cef6ffb0	A64: Implement ADD_shifted	2020-04-22 20:42:44 +01:00
MerryMage	e161cf16f5	A64: Initial framework	2020-04-22 20:42:44 +01:00
MerryMage	f61da0b5a9	IR: Compile-time type-checking of IR	2020-04-22 20:39:27 +01:00
MerryMage	44f7f04b5c	IR/Value: Rename RegRef and ExtRegRef to A32Reg and A32ExtReg	2020-04-22 20:39:27 +01:00
MerryMage	8bef20c24d	IR: Split off A32 specific opcodes	2020-04-22 20:33:32 +01:00
MerryMage	d8a37e287c	IR: Add IR type CoprocInfo	2017-01-08 14:56:06 +00:00
MerryMage	192a0029be	ir/opcodes: Implement IR::AreTypesCompatible Type-checking is now occuring in more than one place.	2016-08-19 01:34:14 +01:00
Tillmann Karras	9782e7da3f	verification_pass: show type errors	2016-08-19 01:17:30 +01:00
MerryMage	1029fd27ce	Update documentation (2016-08-12)	2016-08-12 18:17:31 +01:00
MerryMage	d743adf518	Reorganisation, Import Skyeye, This is a mess	2016-07-04 17:22:11 +08:00