Commit graph

481 commits

Author SHA1 Message Date
MerryMage
95588d3faa Fix Thumb BLX (imm), BL (imm) for negative immediates 2016-07-18 22:48:23 +01:00
MerryMage
3f11a149d7 Implement Thumb Instructions: BLX (imm), BL (imm) 2016-07-18 22:18:58 +01:00
Subv
fce8f75077 Added a dummy (always fail) ARM test about Load/Store instructions that write to the PC. 2016-07-18 16:13:33 -05:00
Subv
426ffc9971 Added ARM fuzz tests for LDRD/LDR/LDRT/LDRB/LDRBT/LDRH and STRD/STR/STRT/STRB/STRBT/STRH.
These tests do not test the behavior of writing to the PC.
2016-07-18 16:13:02 -05:00
Subv
c330d9e0e3 Increase the chance of generating instructions without conditions in the REV/REVSH/REV16 tests. 2016-07-18 16:10:35 -05:00
MerryMage
2363759c62 Implement thumb STM, LDM. Fix thumb POP implementation for P=1. 2016-07-18 20:05:35 +01:00
MerryMage
dfef65d98f Implement thumb POP instruction 2016-07-18 17:37:48 +01:00
MerryMage
f7e3d7b8d2 Implement Thumb PUSH instruction 2016-07-18 15:11:16 +01:00
MerryMage
c18a3eeab4 Better MSVC support
* Avoiding use of templated variables.
* Now compling on MSVC with /WX (warnings as errors).
* Fixed all MSVC warnings.
* Fixed MSVC source_groups.
2016-07-18 10:38:22 +01:00
Subv
0cdf5fe751 Implemented ARM REV and REVSH instructions, with tests. 2016-07-17 14:45:42 -05:00
MerryMage
866dce0f23 tests/Thumb: Add revsh (thumb) test 2016-07-16 19:22:57 +01:00
MerryMage
22b1bd7cc7 tests/Skyeye: Fix thumb REVSH translation 2016-07-16 19:22:09 +01:00
MerryMage
4b1c27e64f Implement arm_ADC_imm 2016-07-14 20:02:41 +01:00
MerryMage
181f78f36e Common: Remove src/common/logging/log.* 2016-07-14 14:55:08 +01:00
MerryMage
07eaf100ba Reorganise src/frontend: Add subdirectories disassembler and translate 2016-07-14 14:39:43 +01:00
MerryMage
672ffb93d0 frontend/translator: Skeleton for Arm translator 2016-07-14 13:28:20 +01:00
MerryMage
8449deb0bc MSVC support 2016-07-12 13:28:09 +01:00
MerryMage
60455f9bbc tests/fuzz_thumb: Fuzz instructions that may change the PC 2016-07-12 10:58:57 +01:00
MerryMage
65d27f3486 tests: Add some Arm tests 2016-07-12 09:12:56 +01:00
MerryMage
1410221b47 Implement thumb1_STR_reg, thumb1_STRH_reg, thumb1_STRB_reg 2016-07-11 23:11:05 +01:00
MerryMage
e7922e4fef Implement thumb1_LDR_literal, thumb1_LDR_imm_t1 2016-07-11 22:43:53 +01:00
MerryMage
d92a771e3c tests/fuzz_thumb: Implement verification of memory writes 2016-07-10 13:29:15 +08:00
MerryMage
8920ce79b9 Implement thumb_CMP_reg_t2 2016-07-10 12:23:16 +08:00
MerryMage
3f7290db16 tests/fuzz_thumb: Change how test instructions are generated (Introduce InstructionGenerator struct) 2016-07-10 12:17:02 +08:00
MerryMage
0a1f153805 tests/fuzz_thumb: Don't poison memory as that slows down tests tremendously 2016-07-08 21:43:28 +08:00
MerryMage
8a0511d297 Implement thumb1_AND_reg 2016-07-08 17:44:53 +08:00
MerryMage
e5f6450a24 Start implementing Thumb disassembler 2016-07-07 21:51:47 +08:00
MerryMage
f31b530703 Fuzz thumb instructions 2016-07-07 19:01:47 +08:00
MerryMage
5711e62419 Implement terminal instructions 2016-07-07 17:53:09 +08:00
MerryMage
14388ea690 Proper implementation of Arm::Translate 2016-07-04 21:37:50 +08:00
MerryMage
d743adf518 Reorganisation, Import Skyeye, This is a mess 2016-07-04 17:22:11 +08:00