From fe71cc9d78cc904360e57303109e8771fe6a42ce Mon Sep 17 00:00:00 2001 From: Tillmann Karras Date: Sun, 31 Jul 2016 19:09:25 +0100 Subject: [PATCH] Disassemble reg-shifted regs in lower case --- src/frontend/disassembler/disassembler_arm.cpp | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/frontend/disassembler/disassembler_arm.cpp b/src/frontend/disassembler/disassembler_arm.cpp index 77985a9a..ec361742 100644 --- a/src/frontend/disassembler/disassembler_arm.cpp +++ b/src/frontend/disassembler/disassembler_arm.cpp @@ -54,13 +54,13 @@ public: std::string RsrStr(Reg s, ShiftType shift, Reg m) { switch (shift){ case ShiftType::LSL: - return Common::StringFromFormat("%s, LSL %s", RegToString(m), RegToString(s)); + return Common::StringFromFormat("%s, lsl %s", RegToString(m), RegToString(s)); case ShiftType::LSR: - return Common::StringFromFormat("%s, LSR %s", RegToString(m), RegToString(s)); + return Common::StringFromFormat("%s, lsr %s", RegToString(m), RegToString(s)); case ShiftType::ASR: - return Common::StringFromFormat("%s, ASR %s", RegToString(m), RegToString(s)); + return Common::StringFromFormat("%s, asr %s", RegToString(m), RegToString(s)); case ShiftType::ROR: - return Common::StringFromFormat("%s, ROR %s", RegToString(m), RegToString(s)); + return Common::StringFromFormat("%s, ror %s", RegToString(m), RegToString(s)); } assert(false); return "";