Ranged cache invalidation
This commit is contained in:
parent
d9c69ad997
commit
fd068ed6b8
11 changed files with 188 additions and 31 deletions
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@ -8,8 +8,8 @@
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#include <cstddef>
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#include <cstdint>
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#include <string>
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#include <memory>
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#include <string>
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#include <dynarmic/callbacks.h>
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@ -38,6 +38,13 @@ public:
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*/
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void ClearCache();
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/**
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* Invalidate the code cache at a range of addresses.
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* @param start_address The starting address of the range to invalidate.
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* @param length The length (in bytes) of the range to invalidate.
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*/
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void InvalidateCacheRange(std::uint32_t start_address, std::size_t length);
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/**
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* Reset CPU state to state at startup. Does not clear code cache.
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* Cannot be called from a callback.
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@ -39,6 +39,7 @@ set(HEADERS
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../include/dynarmic/coprocessor_util.h
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../include/dynarmic/disassembler.h
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../include/dynarmic/dynarmic.h
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common/address_range.h
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common/assert.h
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common/bit_util.h
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common/common_types.h
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@ -12,8 +12,10 @@
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#include "backend_x64/block_of_code.h"
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#include "backend_x64/emit_x64.h"
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#include "backend_x64/jitstate.h"
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#include "common/address_range.h"
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#include "common/assert.h"
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#include "common/bit_util.h"
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#include "common/common_types.h"
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#include "common/variant_util.h"
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#include "frontend/arm/types.h"
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#include "frontend/ir/basic_block.h"
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@ -74,8 +76,9 @@ EmitX64::EmitX64(BlockOfCode* code, UserCallbacks cb, Jit* jit_interface)
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EmitX64::BlockDescriptor EmitX64::Emit(IR::Block& block) {
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code->align();
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const u8* const emitted_code_start_ptr = code->getCurr();
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const u8* const entrypoint = code->getCurr();
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// Start emitting.
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EmitCondPrelude(block);
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RegAlloc reg_alloc{code};
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@ -108,11 +111,12 @@ EmitX64::BlockDescriptor EmitX64::Emit(IR::Block& block) {
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code->int3();
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const IR::LocationDescriptor descriptor = block.Location();
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Patch(descriptor, emitted_code_start_ptr);
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Patch(descriptor, entrypoint);
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const size_t size = static_cast<size_t>(code->getCurr() - entrypoint);
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EmitX64::BlockDescriptor block_desc{entrypoint, size, block.Location(), block.EndLocation().PC()};
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block_descriptors.emplace(descriptor.UniqueHash(), block_desc);
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EmitX64::BlockDescriptor& block_desc = block_descriptors[descriptor.UniqueHash()];
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size_t emitted_code_size = static_cast<size_t>(code->getCurr() - emitted_code_start_ptr);
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block_desc = {emitted_code_start_ptr, emitted_code_size};
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return block_desc;
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}
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@ -459,7 +463,7 @@ void EmitX64::EmitPushRSB(RegAlloc& reg_alloc, IR::Block&, IR::Inst* inst) {
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auto iter = block_descriptors.find(unique_hash_of_target);
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CodePtr target_code_ptr = iter != block_descriptors.end()
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? iter->second.code_ptr
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? iter->second.entrypoint
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: code->GetReturnFromRunCodeAddress();
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Xbyak::Reg64 code_ptr_reg = reg_alloc.ScratchGpr({HostLoc::RCX});
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@ -3345,7 +3349,7 @@ void EmitX64::EmitTerminal(IR::Term::LinkBlock terminal, IR::LocationDescriptor
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patch_information[terminal.next.UniqueHash()].jg.emplace_back(code->getCurr());
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if (auto next_bb = GetBasicBlock(terminal.next)) {
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EmitPatchJg(next_bb->code_ptr);
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EmitPatchJg(next_bb->entrypoint);
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} else {
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EmitPatchJg();
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}
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@ -3374,7 +3378,7 @@ void EmitX64::EmitTerminal(IR::Term::LinkBlockFast terminal, IR::LocationDescrip
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patch_information[terminal.next.UniqueHash()].jmp.emplace_back(code->getCurr());
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if (auto next_bb = GetBasicBlock(terminal.next)) {
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EmitPatchJmp(terminal.next, next_bb->code_ptr);
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EmitPatchJmp(terminal.next, next_bb->entrypoint);
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} else {
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EmitPatchJmp(terminal.next);
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}
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@ -3475,5 +3479,34 @@ void EmitX64::ClearCache() {
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patch_information.clear();
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}
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void EmitX64::InvalidateCacheRange(const Common::AddressRange& range) {
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// Remove cached block descriptors and patch information overlapping with the given range.
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switch (range.which()) {
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case 0: // FullAddressRange
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ClearCache();
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break;
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case 1: // AddressInterval
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auto interval = boost::get<Common::AddressInterval>(range);
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for (auto it = std::begin(block_descriptors); it != std::end(block_descriptors);) {
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const IR::LocationDescriptor& descriptor = it->second.start_location;
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u32 start = descriptor.PC();
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u32 end = it->second.end_location_pc;
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if (interval.Overlaps(start, end)) {
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it = block_descriptors.erase(it);
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auto patch_it = patch_information.find(descriptor.UniqueHash());
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if (patch_it != patch_information.end()) {
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Unpatch(descriptor);
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}
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} else {
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++it;
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}
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}
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break;
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}
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}
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} // namespace BackendX64
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} // namespace Dynarmic
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@ -14,6 +14,7 @@
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#include <xbyak_util.h>
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#include "backend_x64/reg_alloc.h"
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#include "common/address_range.h"
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#include "dynarmic/callbacks.h"
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#include "frontend/ir/location_descriptor.h"
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#include "frontend/ir/terminal.h"
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@ -34,8 +35,11 @@ class BlockOfCode;
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class EmitX64 final {
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public:
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struct BlockDescriptor {
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CodePtr code_ptr; ///< Entrypoint of emitted code
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size_t size; ///< Length in bytes of emitted code
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CodePtr entrypoint; // Entrypoint of emitted code
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size_t size; // Length in bytes of emitted code
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IR::LocationDescriptor start_location;
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u32 end_location_pc;
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};
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EmitX64(BlockOfCode* code, UserCallbacks cb, Jit* jit_interface);
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@ -49,9 +53,16 @@ public:
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/// Looks up an emitted host block in the cache.
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boost::optional<BlockDescriptor> GetBasicBlock(IR::LocationDescriptor descriptor) const;
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/// Empties the cache.
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/// Empties the entire cache.
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void ClearCache();
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/**
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* Invalidate the cache at a range of addresses.
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* @param start_address The starting address of the range to invalidate.
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* @param length The length (in bytes) of the range to invalidate.
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*/
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void InvalidateCacheRange(const Common::AddressRange& range);
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private:
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// Microinstruction emitters
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#define OPCODE(name, type, ...) void Emit##name(RegAlloc& reg_alloc, IR::Block& block, IR::Inst* inst);
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@ -5,6 +5,7 @@
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*/
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#include <memory>
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#include <queue>
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#include <fmt/format.h>
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@ -35,6 +36,7 @@ struct Jit::Impl {
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, jit_state()
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, emitter(&block_of_code, callbacks, jit)
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, callbacks(callbacks)
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, jit_interface(jit)
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{}
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BlockOfCode block_of_code;
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EmitX64 emitter;
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const UserCallbacks callbacks;
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bool clear_cache_required = false;
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// Requests made during execution to invalidate the cache are queued up here.
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std::queue<Common::AddressRange> invalid_cache_ranges;
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size_t Execute(size_t cycle_count) {
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u32 pc = jit_state.Reg[15];
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IR::LocationDescriptor descriptor{pc, Arm::PSR{jit_state.Cpsr}, Arm::FPSCR{jit_state.FPSCR_mode}};
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CodePtr code_ptr = GetBasicBlock(descriptor).code_ptr;
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return block_of_code.RunCode(&jit_state, code_ptr, cycle_count);
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CodePtr entrypoint = GetBasicBlock(descriptor).entrypoint;
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return block_of_code.RunCode(&jit_state, entrypoint, cycle_count);
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}
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std::string Disassemble(const IR::LocationDescriptor& descriptor) {
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auto block = GetBasicBlock(descriptor);
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std::string result = fmt::format("address: {}\nsize: {} bytes\n", block.code_ptr, block.size);
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std::string result = fmt::format("address: {}\nsize: {} bytes\n", block.entrypoint, block.size);
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#ifdef DYNARMIC_USE_LLVM
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LLVMInitializeX86TargetInfo();
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LLVMDisasmContextRef llvm_ctx = LLVMCreateDisasm("x86_64", nullptr, 0, nullptr, nullptr);
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LLVMSetDisasmOptions(llvm_ctx, LLVMDisassembler_Option_AsmPrinterVariant);
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const u8* pos = static_cast<const u8*>(block.code_ptr);
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const u8* pos = static_cast<const u8*>(block.entrypoint);
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const u8* end = pos + block.size;
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size_t remaining = block.size;
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return result;
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}
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void ClearCache() {
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block_of_code.ClearCache();
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emitter.ClearCache();
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void PerformCacheInvalidation() {
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if (invalid_cache_ranges.empty()) {
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return;
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}
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jit_state.ResetRSB();
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clear_cache_required = false;
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block_of_code.ClearCache();
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while (!invalid_cache_ranges.empty()) {
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emitter.InvalidateCacheRange(invalid_cache_ranges.front());
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invalid_cache_ranges.pop();
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}
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}
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void HandleNewCacheRange() {
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if (jit_interface->is_executing) {
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jit_state.halt_requested = true;
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return;
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}
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PerformCacheInvalidation();
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}
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private:
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Jit* jit_interface;
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EmitX64::BlockDescriptor GetBasicBlock(IR::LocationDescriptor descriptor) {
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auto block = emitter.GetBasicBlock(descriptor);
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if (block)
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cycles_executed += impl->Execute(cycle_count - cycles_executed);
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}
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if (impl->clear_cache_required) {
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impl->ClearCache();
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}
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impl->PerformCacheInvalidation();
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return cycles_executed;
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}
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void Jit::ClearCache() {
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if (is_executing) {
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impl->jit_state.halt_requested = true;
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impl->clear_cache_required = true;
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return;
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impl->invalid_cache_ranges.push(Common::FullAddressRange{});
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impl->HandleNewCacheRange();
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}
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impl->ClearCache();
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void Jit::InvalidateCacheRange(std::uint32_t start_address, std::size_t length) {
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impl->invalid_cache_ranges.push(Common::AddressInterval{start_address, length});
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impl->HandleNewCacheRange();
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}
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void Jit::Reset() {
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33
src/common/address_range.h
Normal file
33
src/common/address_range.h
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/* This file is part of the dynarmic project.
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* Copyright (c) 2016 MerryMage
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* This software may be used and distributed according to the terms of the GNU
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* General Public License version 2 or any later version.
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*/
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#pragma once
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#include <cstddef>
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#include <boost/variant.hpp>
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#include "common/common_types.h"
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namespace Dynarmic {
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namespace Common {
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struct FullAddressRange {};
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struct AddressInterval {
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u32 start_address;
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std::size_t length;
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// Does this interval overlap with [from, to)?
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bool Overlaps(u32 from, u32 to) const {
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return start_address <= to && from <= start_address + length;
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}
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};
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using AddressRange = boost::variant<FullAddressRange, AddressInterval>;
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} // namespace Common
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} // namespace Dynarmic
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@ -35,6 +35,14 @@ LocationDescriptor Block::Location() const {
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return location;
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}
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LocationDescriptor Block::EndLocation() const {
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return end_location;
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}
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void Block::SetEndLocation(const LocationDescriptor& descriptor) {
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end_location = descriptor;
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}
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Arm::Cond Block::GetCondition() const {
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return cond;
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}
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using reverse_iterator = InstructionList::reverse_iterator;
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using const_reverse_iterator = InstructionList::const_reverse_iterator;
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explicit Block(const LocationDescriptor& location) : location(location) {}
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explicit Block(const LocationDescriptor& location)
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: location(location), end_location(location) {}
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bool empty() const { return instructions.empty(); }
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size_type size() const { return instructions.size(); }
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/// Gets the starting location for this basic block.
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LocationDescriptor Location() const;
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/// Gets the end location for this basic block.
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LocationDescriptor EndLocation() const;
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/// Sets the end location for this basic block.
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void SetEndLocation(const LocationDescriptor& descriptor);
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/// Gets the condition required to pass in order to execute this block.
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Arm::Cond GetCondition() const;
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private:
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/// Description of the starting location of this block
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LocationDescriptor location;
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/// Description of the end location of this block
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LocationDescriptor end_location;
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/// Conditional to pass in order to execute this block
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Arm::Cond cond = Arm::Cond::AL;
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/// Block to execute next if `cond` did not pass.
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@ -60,6 +60,8 @@ IR::Block TranslateArm(IR::LocationDescriptor descriptor, MemoryReadCodeFuncType
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ASSERT_MSG(visitor.ir.block.HasTerminal(), "Terminal has not been set");
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visitor.ir.block.SetEndLocation(visitor.ir.current_location);
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return std::move(visitor.ir.block);
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}
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@ -909,6 +909,8 @@ IR::Block TranslateThumb(IR::LocationDescriptor descriptor, MemoryReadCodeFuncTy
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visitor.ir.block.CycleCount()++;
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}
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visitor.ir.block.SetEndLocation(visitor.ir.current_location);
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return std::move(visitor.ir.block);
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}
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@ -1166,3 +1166,38 @@ TEST_CASE("Fuzz ARM packing instructions", "[JitX64]") {
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});
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}
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}
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TEST_CASE("arm: Test InvalidateCacheRange", "[arm]") {
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Dynarmic::Jit jit{GetUserCallbacks()};
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code_mem.fill({});
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code_mem[0] = 0xe3a00005; // mov r0, #5
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code_mem[1] = 0xe3a0100D; // mov r1, #13
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code_mem[2] = 0xe0812000; // add r2, r1, r0
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code_mem[3] = 0xeafffffe; // b +#0 (infinite loop)
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jit.Regs() = {};
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jit.Cpsr() = 0x000001d0; // User-mode
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jit.Run(4);
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REQUIRE(jit.Regs()[0] == 5);
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REQUIRE(jit.Regs()[1] == 13);
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REQUIRE(jit.Regs()[2] == 18);
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REQUIRE(jit.Regs()[15] == 0x0000000c);
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REQUIRE(jit.Cpsr() == 0x000001d0);
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// Change the code
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code_mem[1] = 0xe3a01007; // mov r1, #7
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jit.InvalidateCacheRange(/*start_memory_location = */ 4, /* length_in_bytes = */ 4);
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// Reset position of PC
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jit.Regs()[15] = 0;
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jit.Run(4);
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REQUIRE(jit.Regs()[0] == 5);
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REQUIRE(jit.Regs()[1] == 7);
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REQUIRE(jit.Regs()[2] == 12);
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REQUIRE(jit.Regs()[15] == 0x0000000c);
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REQUIRE(jit.Cpsr() == 0x000001d0);
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}
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