From f745eb28bf80cb0b7c4b1d08eb2f559f752fb0c4 Mon Sep 17 00:00:00 2001
From: Lioncash <mathew1800@gmail.com>
Date: Tue, 8 May 2018 11:53:59 -0400
Subject: [PATCH] simd_two_register_misc: Handle 64-bit case for SCVTF_int_4

---
 src/frontend/A64/translate/impl/simd_two_register_misc.cpp | 7 +------
 1 file changed, 1 insertion(+), 6 deletions(-)

diff --git a/src/frontend/A64/translate/impl/simd_two_register_misc.cpp b/src/frontend/A64/translate/impl/simd_two_register_misc.cpp
index 07a23b8c..f0300fb3 100644
--- a/src/frontend/A64/translate/impl/simd_two_register_misc.cpp
+++ b/src/frontend/A64/translate/impl/simd_two_register_misc.cpp
@@ -267,15 +267,10 @@ bool TranslatorVisitor::SCVTF_int_4(bool Q, bool sz, Vec Vn, Vec Vd) {
         return ReservedValue();
     }
 
-    if (sz) {
-        // TODO: Implement
-        return InterpretThisInstruction();
-    }
-
     const size_t datasize = Q ? 128 : 64;
 
     const IR::U128 operand = V(datasize, Vn);
-    const IR::U128 result = ir.FPVectorS32ToSingle(operand);
+    const IR::U128 result = sz ? ir.FPVectorS64ToDouble(operand) : ir.FPVectorS32ToSingle(operand);
 
     V(datasize, Vd, result);
     return true;