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A64: Implement FRECPE, vector single/double variant

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This commit is contained in:
MerryMage 2018-07-25 18:55:58 +01:00
parent 939f5f5c7a
commit f66f61d8ab
2 changed files with 16 additions and 1 deletions
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2
src/frontend/A64/decoder/a64.inc
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@ -612,7 +612,7 @@ INST(FABS_2, "FABS (vector)", "0Q001
//INST(FCVTZS_int_4, "FCVTZS (vector, integer)", "0Q0011101z100001101110nnnnnddddd")
//INST(URECPE, "URECPE", "0Q0011101z100001110010nnnnnddddd")
//INST(FRECPE_3, "FRECPE", "0Q00111011111001110110nnnnnddddd")
//INST(FRECPE_4, "FRECPE", "0Q0011101z100001110110nnnnnddddd")
INST(FRECPE_4, "FRECPE", "0Q0011101z100001110110nnnnnddddd")
INST(REV32_asimd, "REV32 (vector)", "0Q101110zz100000000010nnnnnddddd")
INST(UADDLP, "UADDLP", "0Q101110zz100000001010nnnnnddddd")
//INST(USQADD_2, "USQADD", "0Q101110zz100000001110nnnnnddddd")

15
src/frontend/A64/translate/impl/simd_two_register_misc.cpp
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@ -234,6 +234,21 @@ bool TranslatorVisitor::FCMLT_4(bool Q, bool sz, Vec Vn, Vec Vd) {
return FPCompareAgainstZero(*this, Q, sz, Vn, Vd, ComparisonType::LT);
}
bool TranslatorVisitor::FRECPE_4(bool Q, bool sz, Vec Vn, Vec Vd) {
if (sz && !Q) {
return ReservedValue();
}
const size_t datasize = Q ? 128 : 64;
const size_t esize = sz ? 64 : 32;
const IR::U128 operand = V(datasize, Vn);
const IR::U128 result = ir.FPVectorRecipEstimate(esize, operand);
V(datasize, Vd, result);
return true;
}
bool TranslatorVisitor::FRSQRTE_4(bool Q, bool sz, Vec Vn, Vec Vd) {
if (sz && !Q) {
return ReservedValue();