Merge pull request #499 from lioncash/movw
A32: Implement ARM-mode MOVW
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commit
f4990a5f6b
4 changed files with 21 additions and 0 deletions
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@ -179,6 +179,7 @@ INST(arm_BFC, "BFC", "cccc0111110vvvvvddddvvvvv0011111
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INST(arm_BFI, "BFI", "cccc0111110vvvvvddddvvvvv001nnnn") // v6T2
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INST(arm_CLZ, "CLZ", "cccc000101101111dddd11110001mmmm") // v5
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INST(arm_MOVT, "MOVT", "cccc00110100vvvvddddvvvvvvvvvvvv") // v6T2
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INST(arm_MOVW, "MOVW", "cccc00110000vvvvddddvvvvvvvvvvvv") // v6T2
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INST(arm_NOP, "NOP", "----0011001000001111000000000000") // v6K
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INST(arm_SBFX, "SBFX", "cccc0111101wwwwwddddvvvvv101nnnn") // v6T2
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INST(arm_SEL, "SEL", "cccc01101000nnnndddd11111011mmmm") // v6
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@ -820,6 +820,10 @@ public:
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const u32 imm = concatenate(imm4, imm12).ZeroExtend();
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return fmt::format("movt{} {}, #{}", CondToString(cond), d, imm);
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}
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std::string arm_MOVW(Cond cond, Imm<4> imm4, Reg d, Imm<12> imm12) {
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const u32 imm = concatenate(imm4, imm12).ZeroExtend();
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return fmt::format("movw{}, {}, #{}", CondToString(cond), d, imm);
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}
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std::string arm_NOP() {
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return "nop";
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}
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@ -89,6 +89,21 @@ bool ArmTranslatorVisitor::arm_MOVT(Cond cond, Imm<4> imm4, Reg d, Imm<12> imm12
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return true;
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}
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bool ArmTranslatorVisitor::arm_MOVW(Cond cond, Imm<4> imm4, Reg d, Imm<12> imm12) {
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if (d == Reg::PC) {
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return UnpredictableInstruction();
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}
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if (!ConditionPassed(cond)) {
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return true;
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}
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const IR::U32 imm = ir.Imm32(concatenate(imm4, imm12).ZeroExtend());
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ir.SetRegister(d, imm);
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return true;
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}
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// SBFX<c> <Rd>, <Rn>, #<lsb>, #<width>
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bool ArmTranslatorVisitor::arm_SBFX(Cond cond, Imm<5> widthm1, Reg d, Imm<5> lsb, Reg n) {
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if (d == Reg::PC || n == Reg::PC) {
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@ -226,6 +226,7 @@ struct ArmTranslatorVisitor final {
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bool arm_BFI(Cond cond, Imm<5> msb, Reg d, Imm<5> lsb, Reg n);
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bool arm_CLZ(Cond cond, Reg d, Reg m);
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bool arm_MOVT(Cond cond, Imm<4> imm4, Reg d, Imm<12> imm12);
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bool arm_MOVW(Cond cond, Imm<4> imm4, Reg d, Imm<12> imm12);
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bool arm_NOP() { return true; }
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bool arm_RBIT(Cond cond, Reg d, Reg m);
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bool arm_SBFX(Cond cond, Imm<5> widthm1, Reg d, Imm<5> lsb, Reg n);
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