block_of_code: Encapsulate CPU feature detection code
This commit is contained in:
MerryMage
parent
feddf69cb4
commit
f495018f53
14 changed files with 259 additions and 184 deletions
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@ -284,7 +284,7 @@ void A32EmitX64::GenTerminalHandlers() {
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calculate_location_descriptor();
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code.L(rsb_cache_miss);
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code.mov(r12, reinterpret_cast<u64>(fast_dispatch_table.data()));
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if (code.DoesCpuSupport(Xbyak::util::Cpu::tSSE42)) {
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if (code.HasSSE42()) {
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code.crc32(ebp, r12d);
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}
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code.and_(ebp, fast_dispatch_table_mask);
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@ -302,7 +302,7 @@ void A32EmitX64::GenTerminalHandlers() {
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code.align();
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fast_dispatch_table_lookup = code.getCurr<FastDispatchEntry&(*)(u64)>();
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code.mov(code.ABI_PARAM2, reinterpret_cast<u64>(fast_dispatch_table.data()));
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if (code.DoesCpuSupport(Xbyak::util::Cpu::tSSE42)) {
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if (code.HasSSE42()) {
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code.crc32(code.ABI_PARAM1.cvt32(), code.ABI_PARAM2.cvt32());
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}
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code.and_(code.ABI_PARAM1.cvt32(), fast_dispatch_table_mask);
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@ -417,7 +417,7 @@ static u32 GetCpsrImpl(A32JitState* jit_state) {
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}
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void A32EmitX64::EmitA32GetCpsr(A32EmitContext& ctx, IR::Inst* inst) {
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if (code.DoesCpuSupport(Xbyak::util::Cpu::tBMI2)) {
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if (code.HasBMI2()) {
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const Xbyak::Reg32 result = ctx.reg_alloc.ScratchGpr().cvt32();
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const Xbyak::Reg32 tmp = ctx.reg_alloc.ScratchGpr().cvt32();
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const Xbyak::Reg32 tmp2 = ctx.reg_alloc.ScratchGpr().cvt32();
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@ -456,7 +456,7 @@ static void SetCpsrImpl(u32 value, A32JitState* jit_state) {
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void A32EmitX64::EmitA32SetCpsr(A32EmitContext& ctx, IR::Inst* inst) {
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auto args = ctx.reg_alloc.GetArgumentInfo(inst);
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if (code.DoesCpuSupport(Xbyak::util::Cpu::tBMI2)) {
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if (code.HasBMI2()) {
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const Xbyak::Reg32 cpsr = ctx.reg_alloc.UseScratchGpr(args[0]).cvt32();
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const Xbyak::Reg32 tmp = ctx.reg_alloc.ScratchGpr().cvt32();
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const Xbyak::Reg32 tmp2 = ctx.reg_alloc.ScratchGpr().cvt32();
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@ -514,7 +514,7 @@ void A32EmitX64::EmitA32SetCpsrNZCV(A32EmitContext& ctx, IR::Inst* inst) {
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const u32 imm = args[0].GetImmediateU32();
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code.mov(dword[r15 + offsetof(A32JitState, cpsr_nzcv)], NZCV::ToX64(imm));
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} else if (code.DoesCpuSupport(Xbyak::util::Cpu::tBMI2)) {
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} else if (code.HasBMI2()) {
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const Xbyak::Reg32 a = ctx.reg_alloc.UseScratchGpr(args[0]).cvt32();
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const Xbyak::Reg32 b = ctx.reg_alloc.ScratchGpr().cvt32();
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@ -539,7 +539,7 @@ void A32EmitX64::EmitA32SetCpsrNZCVQ(A32EmitContext& ctx, IR::Inst* inst) {
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code.mov(dword[r15 + offsetof(A32JitState, cpsr_nzcv)], NZCV::ToX64(imm));
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code.mov(code.byte[r15 + offsetof(A32JitState, cpsr_q)], u8((imm & 0x08000000) != 0 ? 1 : 0));
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} else if (code.DoesCpuSupport(Xbyak::util::Cpu::tBMI2)) {
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} else if (code.HasBMI2()) {
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const Xbyak::Reg32 a = ctx.reg_alloc.UseScratchGpr(args[0]).cvt32();
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const Xbyak::Reg32 b = ctx.reg_alloc.ScratchGpr().cvt32();
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@ -666,7 +666,7 @@ void A32EmitX64::EmitA32SetGEFlagsCompressed(A32EmitContext& ctx, IR::Inst* inst
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ge |= Common::Bit<16>(imm) ? 0x000000FF : 0;
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code.mov(dword[r15 + offsetof(A32JitState, cpsr_ge)], ge);
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} else if (code.DoesCpuSupport(Xbyak::util::Cpu::tBMI2)) {
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} else if (code.HasBMI2()) {
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const Xbyak::Reg32 a = ctx.reg_alloc.UseScratchGpr(args[0]).cvt32();
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const Xbyak::Reg32 b = ctx.reg_alloc.ScratchGpr().cvt32();
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@ -154,7 +154,7 @@ void A64EmitX64::GenMemory128Accessors() {
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#else
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code.sub(rsp, 8);
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Devirtualize<&A64::UserCallbacks::MemoryRead128>(conf.callbacks).EmitCall(code);
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if (code.DoesCpuSupport(Xbyak::util::Cpu::tSSE41)) {
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if (code.HasSSE41()) {
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code.movq(xmm1, code.ABI_RETURN);
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code.pinsrq(xmm1, code.ABI_RETURN2, 1);
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} else {
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@ -177,7 +177,7 @@ void A64EmitX64::GenMemory128Accessors() {
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code.add(rsp, 8 + 16 + ABI_SHADOW_SPACE);
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#else
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code.sub(rsp, 8);
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if (code.DoesCpuSupport(Xbyak::util::Cpu::tSSE41)) {
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if (code.HasSSE41()) {
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code.movq(code.ABI_PARAM3, xmm1);
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code.pextrq(code.ABI_PARAM4, xmm1, 1);
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} else {
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@ -328,7 +328,7 @@ void A64EmitX64::GenTerminalHandlers() {
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calculate_location_descriptor();
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code.L(rsb_cache_miss);
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code.mov(r12, reinterpret_cast<u64>(fast_dispatch_table.data()));
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if (code.DoesCpuSupport(Xbyak::util::Cpu::tSSE42)) {
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if (code.HasSSE42()) {
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code.crc32(rbx, r12d);
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}
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code.and_(ebp, fast_dispatch_table_mask);
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@ -346,7 +346,7 @@ void A64EmitX64::GenTerminalHandlers() {
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code.align();
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fast_dispatch_table_lookup = code.getCurr<FastDispatchEntry&(*)(u64)>();
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code.mov(code.ABI_PARAM2, reinterpret_cast<u64>(fast_dispatch_table.data()));
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if (code.DoesCpuSupport(Xbyak::util::Cpu::tSSE42)) {
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if (code.HasSSE42()) {
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code.crc32(code.ABI_PARAM1, code.ABI_PARAM2);
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}
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code.and_(code.ABI_PARAM1.cvt32(), fast_dispatch_table_mask);
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@ -61,7 +61,7 @@ void ABI_PushRegistersAndAdjustStack(BlockOfCode& code, size_t frame_size, const
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size_t xmm_offset = frame_info.xmm_offset;
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for (HostLoc xmm : regs) {
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if (HostLocIsXMM(xmm)) {
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if (code.DoesCpuSupport(Xbyak::util::Cpu::tAVX)) {
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if (code.HasAVX()) {
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code.vmovaps(code.xword[rsp + xmm_offset], HostLocToXmm(xmm));
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} else {
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code.movaps(code.xword[rsp + xmm_offset], HostLocToXmm(xmm));
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@ -83,7 +83,7 @@ void ABI_PopRegistersAndAdjustStack(BlockOfCode& code, size_t frame_size, const
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size_t xmm_offset = frame_info.xmm_offset;
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for (HostLoc xmm : regs) {
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if (HostLocIsXMM(xmm)) {
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if (code.DoesCpuSupport(Xbyak::util::Cpu::tAVX)) {
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if (code.HasAVX()) {
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code.vmovaps(HostLocToXmm(xmm), code.xword[rsp + xmm_offset]);
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} else {
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code.movaps(HostLocToXmm(xmm), code.xword[rsp + xmm_offset]);
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@ -315,6 +315,67 @@ void BlockOfCode::EnsurePatchLocationSize(CodePtr begin, size_t size) {
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nop(size - current_size);
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}
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bool BlockOfCode::HasSSSE3() const {
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return DoesCpuSupport(Xbyak::util::Cpu::tSSSE3);
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}
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bool BlockOfCode::HasSSE41() const {
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return DoesCpuSupport(Xbyak::util::Cpu::tSSE41);
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}
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bool BlockOfCode::HasSSE42() const {
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return DoesCpuSupport(Xbyak::util::Cpu::tSSE42);
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}
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bool BlockOfCode::HasPCLMULQDQ() const {
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return DoesCpuSupport(Xbyak::util::Cpu::tPCLMULQDQ);
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}
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bool BlockOfCode::HasAVX() const {
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return DoesCpuSupport(Xbyak::util::Cpu::tAVX);
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}
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bool BlockOfCode::HasF16C() const {
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return DoesCpuSupport(Xbyak::util::Cpu::tF16C);
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}
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bool BlockOfCode::HasAESNI() const {
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return DoesCpuSupport(Xbyak::util::Cpu::tAESNI);
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}
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bool BlockOfCode::HasLZCNT() const {
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return DoesCpuSupport(Xbyak::util::Cpu::tLZCNT);
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}
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bool BlockOfCode::HasBMI1() const {
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return DoesCpuSupport(Xbyak::util::Cpu::tBMI1);
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}
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bool BlockOfCode::HasBMI2() const {
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return DoesCpuSupport(Xbyak::util::Cpu::tBMI2);
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}
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bool BlockOfCode::HasFMA() const {
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return DoesCpuSupport(Xbyak::util::Cpu::tFMA);
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}
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bool BlockOfCode::HasAVX2() const {
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return DoesCpuSupport(Xbyak::util::Cpu::tAVX2);
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}
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bool BlockOfCode::HasAVX512_Skylake() const {
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// The feature set formerly known as AVX3.2. (Introduced with Skylake.)
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return DoesCpuSupport(Xbyak::util::Cpu::tAVX512F)
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&& DoesCpuSupport(Xbyak::util::Cpu::tAVX512CD)
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&& DoesCpuSupport(Xbyak::util::Cpu::tAVX512BW)
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&& DoesCpuSupport(Xbyak::util::Cpu::tAVX512DQ)
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&& DoesCpuSupport(Xbyak::util::Cpu::tAVX512VL);
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}
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bool BlockOfCode::HasAVX512_BITALG() const {
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return DoesCpuSupport(Xbyak::util::Cpu::tAVX512_BITALG);
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}
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bool BlockOfCode::DoesCpuSupport([[maybe_unused]] Xbyak::util::Cpu::Type type) const {
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#ifdef DYNARMIC_ENABLE_CPU_FEATURE_DETECTION
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return cpu_info.has(type);
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@ -138,10 +138,23 @@ public:
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static const std::array<Xbyak::Reg64, 6> ABI_PARAMS;
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#endif
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bool DoesCpuSupport(Xbyak::util::Cpu::Type type) const;
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JitStateInfo GetJitStateInfo() const { return jsi; }
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bool HasSSSE3() const;
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bool HasSSE41() const;
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bool HasSSE42() const;
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bool HasPCLMULQDQ() const;
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bool HasAVX() const;
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bool HasF16C() const;
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bool HasAESNI() const;
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bool HasLZCNT() const;
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bool HasBMI1() const;
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bool HasBMI2() const;
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bool HasFMA() const;
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bool HasAVX2() const;
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bool HasAVX512_Skylake() const;
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bool HasAVX512_BITALG() const;
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private:
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RunCodeCallbacks cb;
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JitStateInfo jsi;
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@ -165,6 +178,7 @@ private:
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void GenRunCode(std::function<void(BlockOfCode&)> rcp);
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Xbyak::util::Cpu cpu_info;
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bool DoesCpuSupport(Xbyak::util::Cpu::Type type) const;
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};
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} // namespace Dynarmic::Backend::X64
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@ -56,7 +56,7 @@ void EmitX64::EmitAESEncryptSingleRound(EmitContext& ctx, IR::Inst* inst) {
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void EmitX64::EmitAESInverseMixColumns(EmitContext& ctx, IR::Inst* inst) {
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auto args = ctx.reg_alloc.GetArgumentInfo(inst);
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if (code.DoesCpuSupport(Xbyak::util::Cpu::tAESNI)) {
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if (code.HasAESNI()) {
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const Xbyak::Xmm data = ctx.reg_alloc.UseScratchXmm(args[0]);
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code.aesimc(data, data);
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@ -19,7 +19,7 @@ namespace CRC32 = Common::Crypto::CRC32;
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static void EmitCRC32Castagnoli(BlockOfCode& code, EmitContext& ctx, IR::Inst* inst, const int data_size) {
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auto args = ctx.reg_alloc.GetArgumentInfo(inst);
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if (code.DoesCpuSupport(Xbyak::util::Cpu::tSSE42)) {
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if (code.HasSSE42()) {
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const Xbyak::Reg32 crc = ctx.reg_alloc.UseScratchGpr(args[0]).cvt32();
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const Xbyak::Reg value = ctx.reg_alloc.UseGpr(args[1]).changeBit(data_size);
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code.crc32(crc, value);
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@ -35,7 +35,7 @@ static void EmitCRC32Castagnoli(BlockOfCode& code, EmitContext& ctx, IR::Inst* i
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static void EmitCRC32ISO(BlockOfCode& code, EmitContext& ctx, IR::Inst* inst, const int data_size) {
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auto args = ctx.reg_alloc.GetArgumentInfo(inst);
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if (code.DoesCpuSupport(Xbyak::util::Cpu::tPCLMULQDQ) && data_size < 32) {
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if (code.HasPCLMULQDQ() && data_size < 32) {
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const Xbyak::Reg32 crc = ctx.reg_alloc.UseScratchGpr(args[0]).cvt32();
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const Xbyak::Reg64 value = ctx.reg_alloc.UseScratchGpr(args[1]);
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const Xbyak::Xmm xmm_value = ctx.reg_alloc.ScratchXmm();
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@ -49,7 +49,7 @@ static void EmitCRC32ISO(BlockOfCode& code, EmitContext& ctx, IR::Inst* inst, co
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code.movd(xmm_tmp, value.cvt32());
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code.pslldq(xmm_tmp, (64 - data_size) / 8);
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if (code.DoesCpuSupport(Xbyak::util::Cpu::tAVX)) {
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if (code.HasAVX()) {
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code.vpclmulqdq(xmm_value, xmm_tmp, xmm_const, 0x00);
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code.pclmulqdq(xmm_value, xmm_const, 0x10);
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code.pxor(xmm_value, xmm_tmp);
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@ -66,7 +66,7 @@ static void EmitCRC32ISO(BlockOfCode& code, EmitContext& ctx, IR::Inst* inst, co
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return;
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}
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if (code.DoesCpuSupport(Xbyak::util::Cpu::tPCLMULQDQ) && data_size == 32) {
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if (code.HasPCLMULQDQ() && data_size == 32) {
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const Xbyak::Reg32 crc = ctx.reg_alloc.UseScratchGpr(args[0]).cvt32();
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const Xbyak::Reg32 value = ctx.reg_alloc.UseGpr(args[1]).cvt32();
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const Xbyak::Xmm xmm_value = ctx.reg_alloc.ScratchXmm();
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@ -87,7 +87,7 @@ static void EmitCRC32ISO(BlockOfCode& code, EmitContext& ctx, IR::Inst* inst, co
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return;
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}
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if (code.DoesCpuSupport(Xbyak::util::Cpu::tPCLMULQDQ) && data_size == 64) {
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if (code.HasPCLMULQDQ() && data_size == 64) {
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const Xbyak::Reg32 crc = ctx.reg_alloc.UseScratchGpr(args[0]).cvt32();
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const Xbyak::Reg64 value = ctx.reg_alloc.UseGpr(args[1]);
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const Xbyak::Xmm xmm_value = ctx.reg_alloc.ScratchXmm();
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@ -36,7 +36,7 @@ void EmitX64::EmitPack2x64To1x128(EmitContext& ctx, IR::Inst* inst) {
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const Xbyak::Reg64 hi = ctx.reg_alloc.UseGpr(args[1]);
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const Xbyak::Xmm result = ctx.reg_alloc.ScratchXmm();
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if (code.DoesCpuSupport(Xbyak::util::Cpu::tSSE41)) {
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if (code.HasSSE41()) {
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code.movq(result, lo);
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code.pinsrq(result, hi, 1);
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} else {
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@ -791,7 +791,7 @@ static void EmitMaskedShift32(BlockOfCode& code, EmitContext& ctx, IR::Inst* ins
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}
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if constexpr (!std::is_same_v<BMI2FT, std::nullptr_t>) {
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if (code.DoesCpuSupport(Xbyak::util::Cpu::tBMI2)) {
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if (code.HasBMI2()) {
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const Xbyak::Reg32 result = ctx.reg_alloc.ScratchGpr().cvt32();
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const Xbyak::Reg32 operand = ctx.reg_alloc.UseGpr(operand_arg).cvt32();
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const Xbyak::Reg32 shift = ctx.reg_alloc.UseGpr(shift_arg).cvt32();
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@ -828,7 +828,7 @@ static void EmitMaskedShift64(BlockOfCode& code, EmitContext& ctx, IR::Inst* ins
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}
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if constexpr (!std::is_same_v<BMI2FT, std::nullptr_t>) {
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if (code.DoesCpuSupport(Xbyak::util::Cpu::tBMI2)) {
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if (code.HasBMI2()) {
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const Xbyak::Reg64 result = ctx.reg_alloc.ScratchGpr();
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const Xbyak::Reg64 operand = ctx.reg_alloc.UseGpr(operand_arg);
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const Xbyak::Reg64 shift = ctx.reg_alloc.UseGpr(shift_arg);
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@ -1424,7 +1424,7 @@ void EmitX64::EmitByteReverseDual(EmitContext& ctx, IR::Inst* inst) {
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void EmitX64::EmitCountLeadingZeros32(EmitContext& ctx, IR::Inst* inst) {
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auto args = ctx.reg_alloc.GetArgumentInfo(inst);
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if (code.DoesCpuSupport(Xbyak::util::Cpu::tLZCNT)) {
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if (code.HasLZCNT()) {
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const Xbyak::Reg32 source = ctx.reg_alloc.UseGpr(args[0]).cvt32();
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const Xbyak::Reg32 result = ctx.reg_alloc.ScratchGpr().cvt32();
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@ -1448,7 +1448,7 @@ void EmitX64::EmitCountLeadingZeros32(EmitContext& ctx, IR::Inst* inst) {
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void EmitX64::EmitCountLeadingZeros64(EmitContext& ctx, IR::Inst* inst) {
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auto args = ctx.reg_alloc.GetArgumentInfo(inst);
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if (code.DoesCpuSupport(Xbyak::util::Cpu::tLZCNT)) {
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if (code.HasLZCNT()) {
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const Xbyak::Reg64 source = ctx.reg_alloc.UseGpr(args[0]).cvt64();
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const Xbyak::Reg64 result = ctx.reg_alloc.ScratchGpr().cvt64();
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@ -93,7 +93,7 @@ void DenormalsAreZero(BlockOfCode& code, EmitContext& ctx, std::initializer_list
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code.andps(xmm0, xmm);
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if constexpr (fsize == 32) {
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code.pcmpgtd(xmm0, code.MConst(xword, f32_smallest_normal - 1));
|
||||
} else if (code.DoesCpuSupport(Xbyak::util::Cpu::tSSE42)) {
|
||||
} else if (code.HasSSE42()) {
|
||||
code.pcmpgtq(xmm0, code.MConst(xword, f64_smallest_normal - 1));
|
||||
} else {
|
||||
code.pcmpgtd(xmm0, code.MConst(xword, f64_smallest_normal - 1));
|
||||
|
|
@ -114,7 +114,7 @@ void ZeroIfNaN(BlockOfCode& code, Xbyak::Xmm xmm_value, Xbyak::Xmm xmm_scratch)
|
|||
|
||||
template<size_t fsize>
|
||||
void ForceToDefaultNaN(BlockOfCode& code, Xbyak::Xmm result) {
|
||||
if (code.DoesCpuSupport(Xbyak::util::Cpu::tAVX)) {
|
||||
if (code.HasAVX()) {
|
||||
FCODE(vcmpunords)(xmm0, result, result);
|
||||
FCODE(blendvp)(result, code.MConst(xword, fsize == 32 ? f32_nan : f64_nan));
|
||||
} else {
|
||||
|
|
@ -202,7 +202,7 @@ void EmitPostProcessNaNs(BlockOfCode& code, Xbyak::Xmm result, Xbyak::Xmm op1, X
|
|||
// op1 == QNaN && op2 == QNaN is the most common case. With this method
|
||||
// that case would only require one branch.
|
||||
|
||||
if (code.DoesCpuSupport(Xbyak::util::Cpu::tAVX)) {
|
||||
if (code.HasAVX()) {
|
||||
code.vxorps(xmm0, op1, op2);
|
||||
} else {
|
||||
code.movaps(xmm0, op1);
|
||||
|
|
@ -237,7 +237,7 @@ void EmitPostProcessNaNs(BlockOfCode& code, Xbyak::Xmm result, Xbyak::Xmm op1, X
|
|||
code.jna(end, code.T_NEAR);
|
||||
|
||||
// Silence the SNaN as required by spec.
|
||||
if (code.DoesCpuSupport(Xbyak::util::Cpu::tAVX)) {
|
||||
if (code.HasAVX()) {
|
||||
code.vorps(result, op2, code.MConst(xword, mantissa_msb));
|
||||
} else {
|
||||
code.movaps(result, op2);
|
||||
|
|
@ -589,7 +589,7 @@ static void EmitFPMulAdd(BlockOfCode& code, EmitContext& ctx, IR::Inst* inst) {
|
|||
using FPT = mp::unsigned_integer_of_size<fsize>;
|
||||
|
||||
if constexpr (fsize != 16) {
|
||||
if (code.DoesCpuSupport(Xbyak::util::Cpu::tFMA)) {
|
||||
if (code.HasFMA()) {
|
||||
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
|
||||
|
||||
Xbyak::Label end, fallback;
|
||||
|
|
@ -682,7 +682,7 @@ static void EmitFPMulX(BlockOfCode& code, EmitContext& ctx, IR::Inst* inst) {
|
|||
|
||||
Xbyak::Label end, nan, op_are_nans;
|
||||
|
||||
if (code.DoesCpuSupport(Xbyak::util::Cpu::tAVX)) {
|
||||
if (code.HasAVX()) {
|
||||
FCODE(vmuls)(result, op1, op2);
|
||||
} else {
|
||||
code.movaps(result, op1);
|
||||
|
|
@ -696,7 +696,7 @@ static void EmitFPMulX(BlockOfCode& code, EmitContext& ctx, IR::Inst* inst) {
|
|||
code.L(nan);
|
||||
FCODE(ucomis)(op1, op2);
|
||||
code.jp(op_are_nans);
|
||||
if (code.DoesCpuSupport(Xbyak::util::Cpu::tAVX)) {
|
||||
if (code.HasAVX()) {
|
||||
code.vxorps(result, op1, op2);
|
||||
} else {
|
||||
code.movaps(result, op1);
|
||||
|
|
@ -772,7 +772,7 @@ static void EmitFPRecipStepFused(BlockOfCode& code, EmitContext& ctx, IR::Inst*
|
|||
using FPT = mp::unsigned_integer_of_size<fsize>;
|
||||
|
||||
if constexpr (fsize != 16) {
|
||||
if (code.DoesCpuSupport(Xbyak::util::Cpu::tFMA)) {
|
||||
if (code.HasFMA()) {
|
||||
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
|
||||
|
||||
Xbyak::Label end, fallback;
|
||||
|
|
@ -833,7 +833,7 @@ static void EmitFPRound(BlockOfCode& code, EmitContext& ctx, IR::Inst* inst, siz
|
|||
const bool exact = inst->GetArg(2).GetU1();
|
||||
const auto round_imm = ConvertRoundingModeToX64Immediate(rounding_mode);
|
||||
|
||||
if (fsize != 16 && code.DoesCpuSupport(Xbyak::util::Cpu::tSSE41) && round_imm && !exact) {
|
||||
if (fsize != 16 && code.HasSSE41() && round_imm && !exact) {
|
||||
if (fsize == 64) {
|
||||
FPTwoOp<64>(code, ctx, inst, [&](Xbyak::Xmm result) {
|
||||
code.roundsd(result, result, *round_imm);
|
||||
|
|
@ -924,7 +924,7 @@ static void EmitFPRSqrtStepFused(BlockOfCode& code, EmitContext& ctx, IR::Inst*
|
|||
using FPT = mp::unsigned_integer_of_size<fsize>;
|
||||
|
||||
if constexpr (fsize != 16) {
|
||||
if (code.DoesCpuSupport(Xbyak::util::Cpu::tFMA) && code.DoesCpuSupport(Xbyak::util::Cpu::tAVX)) {
|
||||
if (code.HasFMA() && code.HasAVX()) {
|
||||
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
|
||||
|
||||
Xbyak::Label end, fallback;
|
||||
|
|
@ -1071,7 +1071,7 @@ void EmitX64::EmitFPHalfToDouble(EmitContext& ctx, IR::Inst* inst) {
|
|||
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
|
||||
const auto rounding_mode = static_cast<FP::RoundingMode>(args[1].GetImmediateU8());
|
||||
|
||||
if (code.DoesCpuSupport(Xbyak::util::Cpu::tF16C) && !ctx.FPCR().AHP() && !ctx.FPCR().FZ16()) {
|
||||
if (code.HasF16C() && !ctx.FPCR().AHP() && !ctx.FPCR().FZ16()) {
|
||||
const Xbyak::Xmm result = ctx.reg_alloc.ScratchXmm();
|
||||
const Xbyak::Xmm value = ctx.reg_alloc.UseXmm(args[0]);
|
||||
|
||||
|
|
@ -1097,7 +1097,7 @@ void EmitX64::EmitFPHalfToSingle(EmitContext& ctx, IR::Inst* inst) {
|
|||
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
|
||||
const auto rounding_mode = static_cast<FP::RoundingMode>(args[1].GetImmediateU8());
|
||||
|
||||
if (code.DoesCpuSupport(Xbyak::util::Cpu::tF16C) && !ctx.FPCR().AHP() && !ctx.FPCR().FZ16()) {
|
||||
if (code.HasF16C() && !ctx.FPCR().AHP() && !ctx.FPCR().FZ16()) {
|
||||
const Xbyak::Xmm result = ctx.reg_alloc.ScratchXmm();
|
||||
const Xbyak::Xmm value = ctx.reg_alloc.UseXmm(args[0]);
|
||||
|
||||
|
|
@ -1144,7 +1144,7 @@ void EmitX64::EmitFPSingleToHalf(EmitContext& ctx, IR::Inst* inst) {
|
|||
const auto rounding_mode = static_cast<FP::RoundingMode>(args[1].GetImmediateU8());
|
||||
const auto round_imm = ConvertRoundingModeToX64Immediate(rounding_mode);
|
||||
|
||||
if (code.DoesCpuSupport(Xbyak::util::Cpu::tF16C) && !ctx.FPCR().AHP() && !ctx.FPCR().FZ16()) {
|
||||
if (code.HasF16C() && !ctx.FPCR().AHP() && !ctx.FPCR().FZ16()) {
|
||||
const Xbyak::Xmm result = ctx.reg_alloc.UseScratchXmm(args[0]);
|
||||
|
||||
if (ctx.FPCR().DN()) {
|
||||
|
|
@ -1209,7 +1209,7 @@ static void EmitFPToFixed(BlockOfCode& code, EmitContext& ctx, IR::Inst* inst) {
|
|||
if constexpr (fsize != 16) {
|
||||
const auto round_imm = ConvertRoundingModeToX64Immediate(rounding_mode);
|
||||
|
||||
if (code.DoesCpuSupport(Xbyak::util::Cpu::tSSE41) && round_imm){
|
||||
if (code.HasSSE41() && round_imm){
|
||||
const Xbyak::Xmm src = ctx.reg_alloc.UseScratchXmm(args[0]);
|
||||
const Xbyak::Xmm scratch = ctx.reg_alloc.ScratchXmm();
|
||||
const Xbyak::Reg64 result = ctx.reg_alloc.ScratchGpr().cvt64();
|
||||
|
|
@ -1387,7 +1387,7 @@ void EmitX64::EmitFPFixedU32ToSingle(EmitContext& ctx, IR::Inst* inst) {
|
|||
const FP::RoundingMode rounding_mode = static_cast<FP::RoundingMode>(args[2].GetImmediateU8());
|
||||
ASSERT(rounding_mode == ctx.FPCR().RMode());
|
||||
|
||||
if (code.DoesCpuSupport(Xbyak::util::Cpu::tAVX512F)) {
|
||||
if (code.HasAVX512_Skylake()) {
|
||||
const Xbyak::Reg64 from = ctx.reg_alloc.UseGpr(args[0]);
|
||||
code.vcvtusi2ss(result, result, from.cvt32());
|
||||
} else {
|
||||
|
|
@ -1470,7 +1470,7 @@ void EmitX64::EmitFPFixedU32ToDouble(EmitContext& ctx, IR::Inst* inst) {
|
|||
const FP::RoundingMode rounding_mode = static_cast<FP::RoundingMode>(args[2].GetImmediateU8());
|
||||
ASSERT(rounding_mode == ctx.FPCR().RMode());
|
||||
|
||||
if (code.DoesCpuSupport(Xbyak::util::Cpu::tAVX512F)) {
|
||||
if (code.HasAVX512_Skylake()) {
|
||||
const Xbyak::Reg64 from = ctx.reg_alloc.UseGpr(args[0]);
|
||||
code.vcvtusi2sd(to, to, from.cvt32());
|
||||
} else {
|
||||
|
|
@ -1497,7 +1497,7 @@ void EmitX64::EmitFPFixedU64ToDouble(EmitContext& ctx, IR::Inst* inst) {
|
|||
const FP::RoundingMode rounding_mode = static_cast<FP::RoundingMode>(args[2].GetImmediateU8());
|
||||
ASSERT(rounding_mode == ctx.FPCR().RMode());
|
||||
|
||||
if (code.DoesCpuSupport(Xbyak::util::Cpu::tAVX512F)) {
|
||||
if (code.HasAVX512_Skylake()) {
|
||||
code.vcvtusi2sd(result, result, from);
|
||||
} else {
|
||||
const Xbyak::Xmm tmp = ctx.reg_alloc.ScratchXmm();
|
||||
|
|
@ -1528,7 +1528,7 @@ void EmitX64::EmitFPFixedU64ToSingle(EmitContext& ctx, IR::Inst* inst) {
|
|||
const FP::RoundingMode rounding_mode = static_cast<FP::RoundingMode>(args[2].GetImmediateU8());
|
||||
ASSERT(rounding_mode == ctx.FPCR().RMode());
|
||||
|
||||
if (code.DoesCpuSupport(Xbyak::util::Cpu::tAVX512F)) {
|
||||
if (code.HasAVX512_Skylake()) {
|
||||
const Xbyak::Reg64 from = ctx.reg_alloc.UseGpr(args[0]);
|
||||
code.vcvtusi2ss(result, result, from);
|
||||
} else {
|
||||
|
|
|
|||
|
|
@ -76,7 +76,7 @@ void EmitX64::EmitPackedAddU16(EmitContext& ctx, IR::Inst* inst) {
|
|||
code.paddw(xmm_a, xmm_b);
|
||||
|
||||
if (ge_inst) {
|
||||
if (code.DoesCpuSupport(Xbyak::util::Cpu::tSSE41)) {
|
||||
if (code.HasSSE41()) {
|
||||
const Xbyak::Xmm xmm_ge = ctx.reg_alloc.ScratchXmm();
|
||||
const Xbyak::Xmm ones = ctx.reg_alloc.ScratchXmm();
|
||||
|
||||
|
|
@ -199,7 +199,7 @@ void EmitX64::EmitPackedSubU16(EmitContext& ctx, IR::Inst* inst) {
|
|||
return;
|
||||
}
|
||||
|
||||
if (code.DoesCpuSupport(Xbyak::util::Cpu::tSSE41)) {
|
||||
if (code.HasSSE41()) {
|
||||
const Xbyak::Xmm xmm_a = ctx.reg_alloc.UseScratchXmm(args[0]);
|
||||
const Xbyak::Xmm xmm_b = ctx.reg_alloc.UseXmm(args[1]);
|
||||
const Xbyak::Xmm xmm_ge = ctx.reg_alloc.ScratchXmm();
|
||||
|
|
@ -673,7 +673,7 @@ void EmitX64::EmitPackedSelect(EmitContext& ctx, IR::Inst* inst) {
|
|||
code.por(from, ge);
|
||||
|
||||
ctx.reg_alloc.DefineValue(inst, from);
|
||||
} else if (code.DoesCpuSupport(Xbyak::util::Cpu::tBMI1)) {
|
||||
} else if (code.HasBMI1()) {
|
||||
const Xbyak::Reg32 ge = ctx.reg_alloc.UseGpr(args[0]).cvt32();
|
||||
const Xbyak::Reg32 to = ctx.reg_alloc.UseScratchGpr(args[1]).cvt32();
|
||||
const Xbyak::Reg32 from = ctx.reg_alloc.UseScratchGpr(args[2]).cvt32();
|
||||
|
|
|
|||
|
|
@ -164,7 +164,7 @@ void EmitX64::EmitVectorGetElement8(EmitContext& ctx, IR::Inst* inst) {
|
|||
const Xbyak::Xmm source = ctx.reg_alloc.UseXmm(args[0]);
|
||||
const Xbyak::Reg32 dest = ctx.reg_alloc.ScratchGpr().cvt32();
|
||||
|
||||
if (code.DoesCpuSupport(Xbyak::util::Cpu::tSSE41)) {
|
||||
if (code.HasSSE41()) {
|
||||
code.pextrb(dest, source, index);
|
||||
} else {
|
||||
code.pextrw(dest, source, index / 2);
|
||||
|
|
@ -204,7 +204,7 @@ void EmitX64::EmitVectorGetElement32(EmitContext& ctx, IR::Inst* inst) {
|
|||
|
||||
const Xbyak::Reg32 dest = ctx.reg_alloc.ScratchGpr().cvt32();
|
||||
|
||||
if (code.DoesCpuSupport(Xbyak::util::Cpu::tSSE41)) {
|
||||
if (code.HasSSE41()) {
|
||||
const Xbyak::Xmm source = ctx.reg_alloc.UseXmm(args[0]);
|
||||
code.pextrd(dest, source, index);
|
||||
} else {
|
||||
|
|
@ -228,7 +228,7 @@ void EmitX64::EmitVectorGetElement64(EmitContext& ctx, IR::Inst* inst) {
|
|||
|
||||
const Xbyak::Reg64 dest = ctx.reg_alloc.ScratchGpr().cvt64();
|
||||
|
||||
if (code.DoesCpuSupport(Xbyak::util::Cpu::tSSE41)) {
|
||||
if (code.HasSSE41()) {
|
||||
const Xbyak::Xmm source = ctx.reg_alloc.UseXmm(args[0]);
|
||||
code.pextrq(dest, source, 1);
|
||||
} else {
|
||||
|
|
@ -246,7 +246,7 @@ void EmitX64::EmitVectorSetElement8(EmitContext& ctx, IR::Inst* inst) {
|
|||
const u8 index = args[1].GetImmediateU8();
|
||||
const Xbyak::Xmm source_vector = ctx.reg_alloc.UseScratchXmm(args[0]);
|
||||
|
||||
if (code.DoesCpuSupport(Xbyak::util::Cpu::tSSE41)) {
|
||||
if (code.HasSSE41()) {
|
||||
const Xbyak::Reg8 source_elem = ctx.reg_alloc.UseGpr(args[2]).cvt8();
|
||||
|
||||
code.pinsrb(source_vector, source_elem.cvt32(), index);
|
||||
|
|
@ -291,7 +291,7 @@ void EmitX64::EmitVectorSetElement32(EmitContext& ctx, IR::Inst* inst) {
|
|||
const u8 index = args[1].GetImmediateU8();
|
||||
const Xbyak::Xmm source_vector = ctx.reg_alloc.UseScratchXmm(args[0]);
|
||||
|
||||
if (code.DoesCpuSupport(Xbyak::util::Cpu::tSSE41)) {
|
||||
if (code.HasSSE41()) {
|
||||
const Xbyak::Reg32 source_elem = ctx.reg_alloc.UseGpr(args[2]).cvt32();
|
||||
|
||||
code.pinsrd(source_vector, source_elem, index);
|
||||
|
|
@ -314,7 +314,7 @@ void EmitX64::EmitVectorSetElement64(EmitContext& ctx, IR::Inst* inst) {
|
|||
const u8 index = args[1].GetImmediateU8();
|
||||
const Xbyak::Xmm source_vector = ctx.reg_alloc.UseScratchXmm(args[0]);
|
||||
|
||||
if (code.DoesCpuSupport(Xbyak::util::Cpu::tSSE41)) {
|
||||
if (code.HasSSE41()) {
|
||||
const Xbyak::Reg64 source_elem = ctx.reg_alloc.UseGpr(args[2]);
|
||||
|
||||
code.pinsrq(source_vector, source_elem, index);
|
||||
|
|
@ -337,7 +337,7 @@ void EmitX64::EmitVectorSetElement64(EmitContext& ctx, IR::Inst* inst) {
|
|||
}
|
||||
|
||||
static void VectorAbs8(BlockOfCode& code, EmitContext& ctx, const Xbyak::Xmm& data) {
|
||||
if (code.DoesCpuSupport(Xbyak::util::Cpu::tSSSE3)) {
|
||||
if (code.HasSSSE3()) {
|
||||
code.pabsb(data, data);
|
||||
} else {
|
||||
const Xbyak::Xmm temp = ctx.reg_alloc.ScratchXmm();
|
||||
|
|
@ -348,7 +348,7 @@ static void VectorAbs8(BlockOfCode& code, EmitContext& ctx, const Xbyak::Xmm& da
|
|||
}
|
||||
|
||||
static void VectorAbs16(BlockOfCode& code, EmitContext& ctx, const Xbyak::Xmm& data) {
|
||||
if (code.DoesCpuSupport(Xbyak::util::Cpu::tSSSE3)) {
|
||||
if (code.HasSSSE3()) {
|
||||
code.pabsw(data, data);
|
||||
} else {
|
||||
const Xbyak::Xmm temp = ctx.reg_alloc.ScratchXmm();
|
||||
|
|
@ -359,7 +359,7 @@ static void VectorAbs16(BlockOfCode& code, EmitContext& ctx, const Xbyak::Xmm& d
|
|||
}
|
||||
|
||||
static void VectorAbs32(BlockOfCode& code, EmitContext& ctx, const Xbyak::Xmm& data) {
|
||||
if (code.DoesCpuSupport(Xbyak::util::Cpu::tSSSE3)) {
|
||||
if (code.HasSSSE3()) {
|
||||
code.pabsd(data, data);
|
||||
} else {
|
||||
const Xbyak::Xmm temp = ctx.reg_alloc.ScratchXmm();
|
||||
|
|
@ -371,7 +371,7 @@ static void VectorAbs32(BlockOfCode& code, EmitContext& ctx, const Xbyak::Xmm& d
|
|||
}
|
||||
|
||||
static void VectorAbs64(BlockOfCode& code, EmitContext& ctx, const Xbyak::Xmm& data) {
|
||||
if (code.DoesCpuSupport(Xbyak::util::Cpu::tAVX512VL)) {
|
||||
if (code.HasAVX512_Skylake()) {
|
||||
code.vpabsq(data, data);
|
||||
} else {
|
||||
const Xbyak::Xmm temp = ctx.reg_alloc.ScratchXmm();
|
||||
|
|
@ -489,7 +489,7 @@ void EmitX64::EmitVectorArithmeticShiftRight64(EmitContext& ctx, IR::Inst* inst)
|
|||
const Xbyak::Xmm result = ctx.reg_alloc.UseScratchXmm(args[0]);
|
||||
const u8 shift_amount = std::min(args[1].GetImmediateU8(), u8(63));
|
||||
|
||||
if (code.DoesCpuSupport(Xbyak::util::Cpu::tAVX512VL)) {
|
||||
if (code.HasAVX512_Skylake()) {
|
||||
code.vpsraq(result, result, shift_amount);
|
||||
} else {
|
||||
const Xbyak::Xmm tmp1 = ctx.reg_alloc.ScratchXmm();
|
||||
|
|
@ -543,7 +543,7 @@ void EmitX64::EmitVectorArithmeticVShift8(EmitContext& ctx, IR::Inst* inst) {
|
|||
}
|
||||
|
||||
void EmitX64::EmitVectorArithmeticVShift16(EmitContext& ctx, IR::Inst* inst) {
|
||||
if (code.DoesCpuSupport(Xbyak::util::Cpu::tAVX512VL) && code.DoesCpuSupport(Xbyak::util::Cpu::tAVX512BW)) {
|
||||
if (code.HasAVX512_Skylake()) {
|
||||
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
|
||||
|
||||
const Xbyak::Xmm result = ctx.reg_alloc.UseScratchXmm(args[0]);
|
||||
|
|
@ -575,7 +575,7 @@ void EmitX64::EmitVectorArithmeticVShift16(EmitContext& ctx, IR::Inst* inst) {
|
|||
}
|
||||
|
||||
void EmitX64::EmitVectorArithmeticVShift32(EmitContext& ctx, IR::Inst* inst) {
|
||||
if (code.DoesCpuSupport(Xbyak::util::Cpu::tAVX2)) {
|
||||
if (code.HasAVX2()) {
|
||||
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
|
||||
|
||||
const Xbyak::Xmm result = ctx.reg_alloc.UseScratchXmm(args[0]);
|
||||
|
|
@ -606,7 +606,7 @@ void EmitX64::EmitVectorArithmeticVShift32(EmitContext& ctx, IR::Inst* inst) {
|
|||
}
|
||||
|
||||
void EmitX64::EmitVectorArithmeticVShift64(EmitContext& ctx, IR::Inst* inst) {
|
||||
if (code.DoesCpuSupport(Xbyak::util::Cpu::tAVX512F) && code.DoesCpuSupport(Xbyak::util::Cpu::tAVX512VL)) {
|
||||
if (code.HasAVX512_Skylake()) {
|
||||
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
|
||||
|
||||
const Xbyak::Xmm result = ctx.reg_alloc.UseScratchXmm(args[0]);
|
||||
|
|
@ -640,10 +640,10 @@ void EmitX64::EmitVectorBroadcastLower8(EmitContext& ctx, IR::Inst* inst) {
|
|||
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
|
||||
const Xbyak::Xmm a = ctx.reg_alloc.UseScratchXmm(args[0]);
|
||||
|
||||
if (code.DoesCpuSupport(Xbyak::util::Cpu::tAVX2)) {
|
||||
if (code.HasAVX2()) {
|
||||
code.vpbroadcastb(a, a);
|
||||
code.vmovq(a, a);
|
||||
} else if (code.DoesCpuSupport(Xbyak::util::Cpu::tSSSE3)) {
|
||||
} else if (code.HasSSSE3()) {
|
||||
const Xbyak::Xmm tmp = ctx.reg_alloc.ScratchXmm();
|
||||
|
||||
code.pxor(tmp, tmp);
|
||||
|
|
@ -679,9 +679,9 @@ void EmitX64::EmitVectorBroadcast8(EmitContext& ctx, IR::Inst* inst) {
|
|||
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
|
||||
const Xbyak::Xmm a = ctx.reg_alloc.UseScratchXmm(args[0]);
|
||||
|
||||
if (code.DoesCpuSupport(Xbyak::util::Cpu::tAVX2)) {
|
||||
if (code.HasAVX2()) {
|
||||
code.vpbroadcastb(a, a);
|
||||
} else if (code.DoesCpuSupport(Xbyak::util::Cpu::tSSSE3)) {
|
||||
} else if (code.HasSSSE3()) {
|
||||
const Xbyak::Xmm tmp = ctx.reg_alloc.ScratchXmm();
|
||||
|
||||
code.pxor(tmp, tmp);
|
||||
|
|
@ -699,7 +699,7 @@ void EmitX64::EmitVectorBroadcast16(EmitContext& ctx, IR::Inst* inst) {
|
|||
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
|
||||
const Xbyak::Xmm a = ctx.reg_alloc.UseScratchXmm(args[0]);
|
||||
|
||||
if (code.DoesCpuSupport(Xbyak::util::Cpu::tAVX2)) {
|
||||
if (code.HasAVX2()) {
|
||||
code.vpbroadcastw(a, a);
|
||||
} else {
|
||||
code.pshuflw(a, a, 0);
|
||||
|
|
@ -713,7 +713,7 @@ void EmitX64::EmitVectorBroadcast32(EmitContext& ctx, IR::Inst* inst) {
|
|||
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
|
||||
const Xbyak::Xmm a = ctx.reg_alloc.UseScratchXmm(args[0]);
|
||||
|
||||
if (code.DoesCpuSupport(Xbyak::util::Cpu::tAVX2)) {
|
||||
if (code.HasAVX2()) {
|
||||
code.vpbroadcastd(a, a);
|
||||
} else {
|
||||
code.pshufd(a, a, 0);
|
||||
|
|
@ -726,7 +726,7 @@ void EmitX64::EmitVectorBroadcast64(EmitContext& ctx, IR::Inst* inst) {
|
|||
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
|
||||
const Xbyak::Xmm a = ctx.reg_alloc.UseScratchXmm(args[0]);
|
||||
|
||||
if (code.DoesCpuSupport(Xbyak::util::Cpu::tAVX2)) {
|
||||
if (code.HasAVX2()) {
|
||||
code.vpbroadcastq(a, a);
|
||||
} else {
|
||||
code.punpcklqdq(a, a);
|
||||
|
|
@ -751,7 +751,7 @@ static void EmitVectorCountLeadingZeros(VectorArray<T>& result, const VectorArra
|
|||
}
|
||||
|
||||
void EmitX64::EmitVectorCountLeadingZeros8(EmitContext& ctx, IR::Inst* inst) {
|
||||
if (code.DoesCpuSupport(Xbyak::util::Cpu::tSSSE3)) {
|
||||
if (code.HasSSSE3()) {
|
||||
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
|
||||
|
||||
const Xbyak::Xmm data = ctx.reg_alloc.UseScratchXmm(args[0]);
|
||||
|
|
@ -780,7 +780,7 @@ void EmitX64::EmitVectorCountLeadingZeros8(EmitContext& ctx, IR::Inst* inst) {
|
|||
}
|
||||
|
||||
void EmitX64::EmitVectorCountLeadingZeros16(EmitContext& ctx, IR::Inst* inst) {
|
||||
if (code.DoesCpuSupport(Xbyak::util::Cpu::tAVX)) {
|
||||
if (code.HasAVX()) {
|
||||
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
|
||||
|
||||
const Xbyak::Xmm data = ctx.reg_alloc.UseScratchXmm(args[0]);
|
||||
|
|
@ -812,7 +812,7 @@ void EmitX64::EmitVectorCountLeadingZeros16(EmitContext& ctx, IR::Inst* inst) {
|
|||
return;
|
||||
}
|
||||
|
||||
if (code.DoesCpuSupport(Xbyak::util::Cpu::tSSSE3)) {
|
||||
if (code.HasSSSE3()) {
|
||||
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
|
||||
|
||||
const Xbyak::Xmm data = ctx.reg_alloc.UseScratchXmm(args[0]);
|
||||
|
|
@ -852,7 +852,7 @@ void EmitX64::EmitVectorCountLeadingZeros16(EmitContext& ctx, IR::Inst* inst) {
|
|||
}
|
||||
|
||||
void EmitX64::EmitVectorCountLeadingZeros32(EmitContext& ctx, IR::Inst* inst) {
|
||||
if (code.DoesCpuSupport(Xbyak::util::Cpu::tAVX512CD) && code.DoesCpuSupport(Xbyak::util::Cpu::tAVX512VL)) {
|
||||
if (code.HasAVX512_Skylake()) {
|
||||
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
|
||||
|
||||
const Xbyak::Xmm data = ctx.reg_alloc.UseScratchXmm(args[0]);
|
||||
|
|
@ -903,7 +903,7 @@ void EmitX64::EmitVectorDeinterleaveEven32(EmitContext& ctx, IR::Inst* inst) {
|
|||
code.pshufd(lhs, lhs, 0b10001000);
|
||||
code.pshufd(rhs, rhs, 0b10001000);
|
||||
|
||||
if (code.DoesCpuSupport(Xbyak::util::Cpu::tSSE41)) {
|
||||
if (code.HasSSE41()) {
|
||||
code.pblendw(lhs, rhs, 0b11110000);
|
||||
} else {
|
||||
code.punpcklqdq(lhs, rhs);
|
||||
|
|
@ -956,7 +956,7 @@ void EmitX64::EmitVectorDeinterleaveOdd32(EmitContext& ctx, IR::Inst* inst) {
|
|||
code.pshufd(lhs, lhs, 0b11011101);
|
||||
code.pshufd(rhs, rhs, 0b11011101);
|
||||
|
||||
if (code.DoesCpuSupport(Xbyak::util::Cpu::tSSE41)) {
|
||||
if (code.HasSSE41()) {
|
||||
code.pblendw(lhs, rhs, 0b11110000);
|
||||
} else {
|
||||
code.punpcklqdq(lhs, rhs);
|
||||
|
|
@ -992,7 +992,7 @@ void EmitX64::EmitVectorEqual32(EmitContext& ctx, IR::Inst* inst) {
|
|||
}
|
||||
|
||||
void EmitX64::EmitVectorEqual64(EmitContext& ctx, IR::Inst* inst) {
|
||||
if (code.DoesCpuSupport(Xbyak::util::Cpu::tSSE41)) {
|
||||
if (code.HasSSE41()) {
|
||||
EmitVectorOperation(code, ctx, inst, &Xbyak::CodeGenerator::pcmpeqq);
|
||||
return;
|
||||
}
|
||||
|
|
@ -1013,7 +1013,7 @@ void EmitX64::EmitVectorEqual64(EmitContext& ctx, IR::Inst* inst) {
|
|||
void EmitX64::EmitVectorEqual128(EmitContext& ctx, IR::Inst* inst) {
|
||||
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
|
||||
|
||||
if (code.DoesCpuSupport(Xbyak::util::Cpu::tSSE41)) {
|
||||
if (code.HasSSE41()) {
|
||||
const Xbyak::Xmm xmm_a = ctx.reg_alloc.UseScratchXmm(args[0]);
|
||||
const Xbyak::Xmm xmm_b = ctx.reg_alloc.UseXmm(args[1]);
|
||||
const Xbyak::Xmm tmp = ctx.reg_alloc.ScratchXmm();
|
||||
|
|
@ -1049,7 +1049,7 @@ void EmitX64::EmitVectorExtract(EmitContext& ctx, IR::Inst* inst) {
|
|||
return;
|
||||
}
|
||||
|
||||
if (code.DoesCpuSupport(Xbyak::util::Cpu::tSSSE3)) {
|
||||
if (code.HasSSSE3()) {
|
||||
const Xbyak::Xmm xmm_a = ctx.reg_alloc.UseXmm(args[0]);
|
||||
const Xbyak::Xmm xmm_b = ctx.reg_alloc.UseScratchXmm(args[1]);
|
||||
|
||||
|
|
@ -1100,7 +1100,7 @@ void EmitX64::EmitVectorGreaterS32(EmitContext& ctx, IR::Inst* inst) {
|
|||
}
|
||||
|
||||
void EmitX64::EmitVectorGreaterS64(EmitContext& ctx, IR::Inst* inst) {
|
||||
if (code.DoesCpuSupport(Xbyak::util::Cpu::tSSE42)) {
|
||||
if (code.HasSSE42()) {
|
||||
EmitVectorOperation(code, ctx, inst, &Xbyak::CodeGenerator::pcmpgtq);
|
||||
return;
|
||||
}
|
||||
|
|
@ -1473,7 +1473,7 @@ void EmitX64::EmitVectorLogicalVShift8(EmitContext& ctx, IR::Inst* inst) {
|
|||
}
|
||||
|
||||
void EmitX64::EmitVectorLogicalVShift16(EmitContext& ctx, IR::Inst* inst) {
|
||||
if (code.DoesCpuSupport(Xbyak::util::Cpu::tAVX512VL) && code.DoesCpuSupport(Xbyak::util::Cpu::tAVX512BW)) {
|
||||
if (code.HasAVX512_Skylake()) {
|
||||
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
|
||||
|
||||
const Xbyak::Xmm result = ctx.reg_alloc.UseScratchXmm(args[0]);
|
||||
|
|
@ -1501,7 +1501,7 @@ void EmitX64::EmitVectorLogicalVShift16(EmitContext& ctx, IR::Inst* inst) {
|
|||
}
|
||||
|
||||
void EmitX64::EmitVectorLogicalVShift32(EmitContext& ctx, IR::Inst* inst) {
|
||||
if (code.DoesCpuSupport(Xbyak::util::Cpu::tAVX2)) {
|
||||
if (code.HasAVX2()) {
|
||||
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
|
||||
|
||||
const Xbyak::Xmm result = ctx.reg_alloc.UseScratchXmm(args[0]);
|
||||
|
|
@ -1529,7 +1529,7 @@ void EmitX64::EmitVectorLogicalVShift32(EmitContext& ctx, IR::Inst* inst) {
|
|||
}
|
||||
|
||||
void EmitX64::EmitVectorLogicalVShift64(EmitContext& ctx, IR::Inst* inst) {
|
||||
if (code.DoesCpuSupport(Xbyak::util::Cpu::tAVX2)) {
|
||||
if (code.HasAVX2()) {
|
||||
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
|
||||
|
||||
const Xbyak::Xmm result = ctx.reg_alloc.UseScratchXmm(args[0]);
|
||||
|
|
@ -1557,7 +1557,7 @@ void EmitX64::EmitVectorLogicalVShift64(EmitContext& ctx, IR::Inst* inst) {
|
|||
}
|
||||
|
||||
void EmitX64::EmitVectorMaxS8(EmitContext& ctx, IR::Inst* inst) {
|
||||
if (code.DoesCpuSupport(Xbyak::util::Cpu::tSSE41)) {
|
||||
if (code.HasSSE41()) {
|
||||
EmitVectorOperation(code, ctx, inst, &Xbyak::CodeGenerator::pmaxsb);
|
||||
return;
|
||||
}
|
||||
|
|
@ -1582,7 +1582,7 @@ void EmitX64::EmitVectorMaxS16(EmitContext& ctx, IR::Inst* inst) {
|
|||
}
|
||||
|
||||
void EmitX64::EmitVectorMaxS32(EmitContext& ctx, IR::Inst* inst) {
|
||||
if (code.DoesCpuSupport(Xbyak::util::Cpu::tSSE41)) {
|
||||
if (code.HasSSE41()) {
|
||||
EmitVectorOperation(code, ctx, inst, &Xbyak::CodeGenerator::pmaxsd);
|
||||
return;
|
||||
}
|
||||
|
|
@ -1603,12 +1603,12 @@ void EmitX64::EmitVectorMaxS32(EmitContext& ctx, IR::Inst* inst) {
|
|||
}
|
||||
|
||||
void EmitX64::EmitVectorMaxS64(EmitContext& ctx, IR::Inst* inst) {
|
||||
if (code.DoesCpuSupport(Xbyak::util::Cpu::tAVX512VL)) {
|
||||
if (code.HasAVX512_Skylake()) {
|
||||
EmitAVXVectorOperation(code, ctx, inst, &Xbyak::CodeGenerator::vpmaxsq);
|
||||
return;
|
||||
}
|
||||
|
||||
if (code.DoesCpuSupport(Xbyak::util::Cpu::tAVX)) {
|
||||
if (code.HasAVX()) {
|
||||
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
|
||||
|
||||
const Xbyak::Xmm x = ctx.reg_alloc.UseScratchXmm(args[0]);
|
||||
|
|
@ -1631,7 +1631,7 @@ void EmitX64::EmitVectorMaxU8(EmitContext& ctx, IR::Inst* inst) {
|
|||
}
|
||||
|
||||
void EmitX64::EmitVectorMaxU16(EmitContext& ctx, IR::Inst* inst) {
|
||||
if (code.DoesCpuSupport(Xbyak::util::Cpu::tSSE41)) {
|
||||
if (code.HasSSE41()) {
|
||||
EmitVectorOperation(code, ctx, inst, &Xbyak::CodeGenerator::pmaxuw);
|
||||
return;
|
||||
}
|
||||
|
|
@ -1647,7 +1647,7 @@ void EmitX64::EmitVectorMaxU16(EmitContext& ctx, IR::Inst* inst) {
|
|||
}
|
||||
|
||||
void EmitX64::EmitVectorMaxU32(EmitContext& ctx, IR::Inst* inst) {
|
||||
if (code.DoesCpuSupport(Xbyak::util::Cpu::tSSE41)) {
|
||||
if (code.HasSSE41()) {
|
||||
EmitVectorOperation(code, ctx, inst, &Xbyak::CodeGenerator::pmaxud);
|
||||
return;
|
||||
}
|
||||
|
|
@ -1674,12 +1674,12 @@ void EmitX64::EmitVectorMaxU32(EmitContext& ctx, IR::Inst* inst) {
|
|||
}
|
||||
|
||||
void EmitX64::EmitVectorMaxU64(EmitContext& ctx, IR::Inst* inst) {
|
||||
if (code.DoesCpuSupport(Xbyak::util::Cpu::tAVX512VL)) {
|
||||
if (code.HasAVX512_Skylake()) {
|
||||
EmitAVXVectorOperation(code, ctx, inst, &Xbyak::CodeGenerator::vpmaxuq);
|
||||
return;
|
||||
}
|
||||
|
||||
if (code.DoesCpuSupport(Xbyak::util::Cpu::tAVX)) {
|
||||
if (code.HasAVX()) {
|
||||
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
|
||||
|
||||
const Xbyak::Xmm x = ctx.reg_alloc.UseScratchXmm(args[0]);
|
||||
|
|
@ -1702,7 +1702,7 @@ void EmitX64::EmitVectorMaxU64(EmitContext& ctx, IR::Inst* inst) {
|
|||
}
|
||||
|
||||
void EmitX64::EmitVectorMinS8(EmitContext& ctx, IR::Inst* inst) {
|
||||
if (code.DoesCpuSupport(Xbyak::util::Cpu::tSSE41)) {
|
||||
if (code.HasSSE41()) {
|
||||
EmitVectorOperation(code, ctx, inst, &Xbyak::CodeGenerator::pminsb);
|
||||
return;
|
||||
}
|
||||
|
|
@ -1727,7 +1727,7 @@ void EmitX64::EmitVectorMinS16(EmitContext& ctx, IR::Inst* inst) {
|
|||
}
|
||||
|
||||
void EmitX64::EmitVectorMinS32(EmitContext& ctx, IR::Inst* inst) {
|
||||
if (code.DoesCpuSupport(Xbyak::util::Cpu::tSSE41)) {
|
||||
if (code.HasSSE41()) {
|
||||
EmitVectorOperation(code, ctx, inst, &Xbyak::CodeGenerator::pminsd);
|
||||
return;
|
||||
}
|
||||
|
|
@ -1748,12 +1748,12 @@ void EmitX64::EmitVectorMinS32(EmitContext& ctx, IR::Inst* inst) {
|
|||
}
|
||||
|
||||
void EmitX64::EmitVectorMinS64(EmitContext& ctx, IR::Inst* inst) {
|
||||
if (code.DoesCpuSupport(Xbyak::util::Cpu::tAVX512VL)) {
|
||||
if (code.HasAVX512_Skylake()) {
|
||||
EmitAVXVectorOperation(code, ctx, inst, &Xbyak::CodeGenerator::vpminsq);
|
||||
return;
|
||||
}
|
||||
|
||||
if (code.DoesCpuSupport(Xbyak::util::Cpu::tAVX)) {
|
||||
if (code.HasAVX()) {
|
||||
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
|
||||
|
||||
const Xbyak::Xmm x = ctx.reg_alloc.UseXmm(args[0]);
|
||||
|
|
@ -1776,7 +1776,7 @@ void EmitX64::EmitVectorMinU8(EmitContext& ctx, IR::Inst* inst) {
|
|||
}
|
||||
|
||||
void EmitX64::EmitVectorMinU16(EmitContext& ctx, IR::Inst* inst) {
|
||||
if (code.DoesCpuSupport(Xbyak::util::Cpu::tSSE41)) {
|
||||
if (code.HasSSE41()) {
|
||||
EmitVectorOperation(code, ctx, inst, &Xbyak::CodeGenerator::pminuw);
|
||||
return;
|
||||
}
|
||||
|
|
@ -1795,7 +1795,7 @@ void EmitX64::EmitVectorMinU16(EmitContext& ctx, IR::Inst* inst) {
|
|||
}
|
||||
|
||||
void EmitX64::EmitVectorMinU32(EmitContext& ctx, IR::Inst* inst) {
|
||||
if (code.DoesCpuSupport(Xbyak::util::Cpu::tSSE41)) {
|
||||
if (code.HasSSE41()) {
|
||||
EmitVectorOperation(code, ctx, inst, &Xbyak::CodeGenerator::pminud);
|
||||
return;
|
||||
}
|
||||
|
|
@ -1824,12 +1824,12 @@ void EmitX64::EmitVectorMinU32(EmitContext& ctx, IR::Inst* inst) {
|
|||
}
|
||||
|
||||
void EmitX64::EmitVectorMinU64(EmitContext& ctx, IR::Inst* inst) {
|
||||
if (code.DoesCpuSupport(Xbyak::util::Cpu::tAVX512VL)) {
|
||||
if (code.HasAVX512_Skylake()) {
|
||||
EmitAVXVectorOperation(code, ctx, inst, &Xbyak::CodeGenerator::vpminuq);
|
||||
return;
|
||||
}
|
||||
|
||||
if (code.DoesCpuSupport(Xbyak::util::Cpu::tAVX)) {
|
||||
if (code.HasAVX()) {
|
||||
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
|
||||
|
||||
const Xbyak::Xmm x = ctx.reg_alloc.UseXmm(args[0]);
|
||||
|
|
@ -1877,7 +1877,7 @@ void EmitX64::EmitVectorMultiply16(EmitContext& ctx, IR::Inst* inst) {
|
|||
}
|
||||
|
||||
void EmitX64::EmitVectorMultiply32(EmitContext& ctx, IR::Inst* inst) {
|
||||
if (code.DoesCpuSupport(Xbyak::util::Cpu::tSSE41)) {
|
||||
if (code.HasSSE41()) {
|
||||
EmitVectorOperation(code, ctx, inst, &Xbyak::CodeGenerator::pmulld);
|
||||
return;
|
||||
}
|
||||
|
|
@ -1900,14 +1900,14 @@ void EmitX64::EmitVectorMultiply32(EmitContext& ctx, IR::Inst* inst) {
|
|||
}
|
||||
|
||||
void EmitX64::EmitVectorMultiply64(EmitContext& ctx, IR::Inst* inst) {
|
||||
if (code.DoesCpuSupport(Xbyak::util::Cpu::tAVX512DQ) && code.DoesCpuSupport(Xbyak::util::Cpu::tAVX512VL)) {
|
||||
if (code.HasAVX512_Skylake()) {
|
||||
EmitAVXVectorOperation(code, ctx, inst, &Xbyak::CodeGenerator::vpmullq);
|
||||
return;
|
||||
}
|
||||
|
||||
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
|
||||
|
||||
if (code.DoesCpuSupport(Xbyak::util::Cpu::tSSE41)) {
|
||||
if (code.HasSSE41()) {
|
||||
const Xbyak::Xmm a = ctx.reg_alloc.UseScratchXmm(args[0]);
|
||||
const Xbyak::Xmm b = ctx.reg_alloc.UseXmm(args[1]);
|
||||
const Xbyak::Reg64 tmp1 = ctx.reg_alloc.ScratchGpr();
|
||||
|
|
@ -1953,7 +1953,7 @@ void EmitX64::EmitVectorMultiply64(EmitContext& ctx, IR::Inst* inst) {
|
|||
void EmitX64::EmitVectorNarrow16(EmitContext& ctx, IR::Inst* inst) {
|
||||
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
|
||||
|
||||
if (code.DoesCpuSupport(Xbyak::util::Cpu::tAVX512VL) && code.DoesCpuSupport(Xbyak::util::Cpu::tAVX512BW)) {
|
||||
if (code.HasAVX512_Skylake()) {
|
||||
const Xbyak::Xmm a = ctx.reg_alloc.UseXmm(args[0]);
|
||||
const Xbyak::Xmm result = ctx.reg_alloc.ScratchXmm();
|
||||
|
||||
|
|
@ -1981,7 +1981,7 @@ void EmitX64::EmitVectorNarrow32(EmitContext& ctx, IR::Inst* inst) {
|
|||
// TODO: AVX512F implementation
|
||||
|
||||
code.pxor(zeros, zeros);
|
||||
if (code.DoesCpuSupport(Xbyak::util::Cpu::tSSE41)) {
|
||||
if (code.HasSSE41()) {
|
||||
code.pblendw(a, zeros, 0b10101010);
|
||||
code.packusdw(a, zeros);
|
||||
} else {
|
||||
|
|
@ -2048,7 +2048,7 @@ void EmitX64::EmitVectorPairedAddLower16(EmitContext& ctx, IR::Inst* inst) {
|
|||
const Xbyak::Xmm tmp = ctx.reg_alloc.ScratchXmm();
|
||||
|
||||
code.punpcklqdq(xmm_a, xmm_b);
|
||||
if (code.DoesCpuSupport(Xbyak::util::Cpu::tSSSE3)) {
|
||||
if (code.HasSSSE3()) {
|
||||
code.pxor(tmp, tmp);
|
||||
code.phaddw(xmm_a, tmp);
|
||||
} else {
|
||||
|
|
@ -2071,7 +2071,7 @@ void EmitX64::EmitVectorPairedAddLower32(EmitContext& ctx, IR::Inst* inst) {
|
|||
const Xbyak::Xmm tmp = ctx.reg_alloc.ScratchXmm();
|
||||
|
||||
code.punpcklqdq(xmm_a, xmm_b);
|
||||
if (code.DoesCpuSupport(Xbyak::util::Cpu::tSSSE3)) {
|
||||
if (code.HasSSSE3()) {
|
||||
code.pxor(tmp, tmp);
|
||||
code.phaddd(xmm_a, tmp);
|
||||
} else {
|
||||
|
|
@ -2109,7 +2109,7 @@ void EmitX64::EmitVectorPairedAdd8(EmitContext& ctx, IR::Inst* inst) {
|
|||
void EmitX64::EmitVectorPairedAdd16(EmitContext& ctx, IR::Inst* inst) {
|
||||
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
|
||||
|
||||
if (code.DoesCpuSupport(Xbyak::util::Cpu::tSSSE3)) {
|
||||
if (code.HasSSSE3()) {
|
||||
const Xbyak::Xmm a = ctx.reg_alloc.UseScratchXmm(args[0]);
|
||||
const Xbyak::Xmm b = ctx.reg_alloc.UseXmm(args[1]);
|
||||
|
||||
|
|
@ -2139,7 +2139,7 @@ void EmitX64::EmitVectorPairedAdd16(EmitContext& ctx, IR::Inst* inst) {
|
|||
void EmitX64::EmitVectorPairedAdd32(EmitContext& ctx, IR::Inst* inst) {
|
||||
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
|
||||
|
||||
if (code.DoesCpuSupport(Xbyak::util::Cpu::tSSSE3)) {
|
||||
if (code.HasSSSE3()) {
|
||||
const Xbyak::Xmm a = ctx.reg_alloc.UseScratchXmm(args[0]);
|
||||
const Xbyak::Xmm b = ctx.reg_alloc.UseXmm(args[1]);
|
||||
|
||||
|
|
@ -2215,7 +2215,7 @@ void EmitX64::EmitVectorPairedAddSignedWiden32(EmitContext& ctx, IR::Inst* inst)
|
|||
const Xbyak::Xmm a = ctx.reg_alloc.UseScratchXmm(args[0]);
|
||||
const Xbyak::Xmm c = ctx.reg_alloc.ScratchXmm();
|
||||
|
||||
if (code.DoesCpuSupport(Xbyak::util::Cpu::tAVX512VL)) {
|
||||
if (code.HasAVX512_Skylake()) {
|
||||
code.vpsraq(c, a, 32);
|
||||
code.vpsllq(a, a, 32);
|
||||
code.vpsraq(a, a, 32);
|
||||
|
|
@ -2332,7 +2332,7 @@ void EmitX64::EmitVectorPairedMaxS32(EmitContext& ctx, IR::Inst* inst) {
|
|||
code.shufps(tmp, y, 0b10001000);
|
||||
code.shufps(x, y, 0b11011101);
|
||||
|
||||
if (code.DoesCpuSupport(Xbyak::util::Cpu::tSSE41)) {
|
||||
if (code.HasSSE41()) {
|
||||
code.pmaxsd(x, tmp);
|
||||
|
||||
ctx.reg_alloc.DefineValue(inst, x);
|
||||
|
|
@ -2372,7 +2372,7 @@ void EmitX64::EmitVectorPairedMaxU32(EmitContext& ctx, IR::Inst* inst) {
|
|||
code.shufps(tmp1, y, 0b10001000);
|
||||
code.shufps(x, y, 0b11011101);
|
||||
|
||||
if (code.DoesCpuSupport(Xbyak::util::Cpu::tSSE41)) {
|
||||
if (code.HasSSE41()) {
|
||||
code.pmaxud(x, tmp1);
|
||||
|
||||
ctx.reg_alloc.DefineValue(inst, x);
|
||||
|
|
@ -2417,7 +2417,7 @@ void EmitX64::EmitVectorPairedMinS32(EmitContext& ctx, IR::Inst* inst) {
|
|||
code.shufps(tmp, y, 0b10001000);
|
||||
code.shufps(x, y, 0b11011101);
|
||||
|
||||
if (code.DoesCpuSupport(Xbyak::util::Cpu::tSSE41)) {
|
||||
if (code.HasSSE41()) {
|
||||
code.pminsd(x, tmp);
|
||||
|
||||
ctx.reg_alloc.DefineValue(inst, x);
|
||||
|
|
@ -2457,7 +2457,7 @@ void EmitX64::EmitVectorPairedMinU32(EmitContext& ctx, IR::Inst* inst) {
|
|||
code.shufps(tmp1, y, 0b10001000);
|
||||
code.shufps(x, y, 0b11011101);
|
||||
|
||||
if (code.DoesCpuSupport(Xbyak::util::Cpu::tSSE41)) {
|
||||
if (code.HasSSE41()) {
|
||||
code.pminud(x, tmp1);
|
||||
|
||||
ctx.reg_alloc.DefineValue(inst, x);
|
||||
|
|
@ -2529,7 +2529,7 @@ void EmitX64::EmitVectorPolynomialMultiplyLong64(EmitContext& ctx, IR::Inst* ins
|
|||
}
|
||||
|
||||
void EmitX64::EmitVectorPopulationCount(EmitContext& ctx, IR::Inst* inst) {
|
||||
if (code.DoesCpuSupport(Xbyak::util::Cpu::tAVX512_BITALG)) {
|
||||
if (code.HasAVX512_BITALG()) {
|
||||
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
|
||||
const Xbyak::Xmm data = ctx.reg_alloc.UseScratchXmm(args[0]);
|
||||
|
||||
|
|
@ -2539,7 +2539,7 @@ void EmitX64::EmitVectorPopulationCount(EmitContext& ctx, IR::Inst* inst) {
|
|||
return;
|
||||
}
|
||||
|
||||
if (code.DoesCpuSupport(Xbyak::util::Cpu::tSSSE3)) {
|
||||
if (code.HasSSSE3()) {
|
||||
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
|
||||
|
||||
const Xbyak::Xmm low_a = ctx.reg_alloc.UseScratchXmm(args[0]);
|
||||
|
|
@ -2582,7 +2582,7 @@ void EmitX64::EmitVectorReverseBits(EmitContext& ctx, IR::Inst* inst) {
|
|||
code.pxor(data, high_nibble_reg);
|
||||
code.psrld(high_nibble_reg, 4);
|
||||
|
||||
if (code.DoesCpuSupport(Xbyak::util::Cpu::tSSSE3)) {
|
||||
if (code.HasSSSE3()) {
|
||||
// High lookup
|
||||
const Xbyak::Xmm high_reversed_reg = ctx.reg_alloc.ScratchXmm();
|
||||
code.movdqa(high_reversed_reg, code.MConst(xword, 0xE060A020C0408000, 0xF070B030D0509010));
|
||||
|
|
@ -2822,7 +2822,7 @@ void EmitX64::EmitVectorShuffleWords(EmitContext& ctx, IR::Inst* inst) {
|
|||
|
||||
void EmitX64::EmitVectorSignExtend8(EmitContext& ctx, IR::Inst* inst) {
|
||||
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
|
||||
if (code.DoesCpuSupport(Xbyak::util::Cpu::tSSE41)) {
|
||||
if (code.HasSSE41()) {
|
||||
const Xbyak::Xmm a = ctx.reg_alloc.UseScratchXmm(args[0]);
|
||||
code.pmovsxbw(a, a);
|
||||
ctx.reg_alloc.DefineValue(inst, a);
|
||||
|
|
@ -2838,7 +2838,7 @@ void EmitX64::EmitVectorSignExtend8(EmitContext& ctx, IR::Inst* inst) {
|
|||
|
||||
void EmitX64::EmitVectorSignExtend16(EmitContext& ctx, IR::Inst* inst) {
|
||||
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
|
||||
if (code.DoesCpuSupport(Xbyak::util::Cpu::tSSE41)) {
|
||||
if (code.HasSSE41()) {
|
||||
const Xbyak::Xmm a = ctx.reg_alloc.UseScratchXmm(args[0]);
|
||||
code.pmovsxwd(a, a);
|
||||
ctx.reg_alloc.DefineValue(inst, a);
|
||||
|
|
@ -2856,7 +2856,7 @@ void EmitX64::EmitVectorSignExtend32(EmitContext& ctx, IR::Inst* inst) {
|
|||
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
|
||||
const Xbyak::Xmm a = ctx.reg_alloc.UseScratchXmm(args[0]);
|
||||
|
||||
if (code.DoesCpuSupport(Xbyak::util::Cpu::tSSE41)) {
|
||||
if (code.HasSSE41()) {
|
||||
code.pmovsxdq(a, a);
|
||||
} else {
|
||||
const Xbyak::Xmm tmp = ctx.reg_alloc.ScratchXmm();
|
||||
|
|
@ -2878,7 +2878,7 @@ void EmitX64::EmitVectorSignExtend64(EmitContext& ctx, IR::Inst* inst) {
|
|||
code.movq(gpr_tmp, data);
|
||||
code.sar(gpr_tmp, 63);
|
||||
|
||||
if (code.DoesCpuSupport(Xbyak::util::Cpu::tSSE41)) {
|
||||
if (code.HasSSE41()) {
|
||||
code.pinsrq(data, gpr_tmp, 1);
|
||||
} else {
|
||||
const Xbyak::Xmm xmm_tmp = ctx.reg_alloc.ScratchXmm();
|
||||
|
|
@ -2949,7 +2949,7 @@ void EmitX64::EmitVectorSignedMultiply16(EmitContext& ctx, IR::Inst* inst) {
|
|||
|
||||
if (upper_inst) {
|
||||
const Xbyak::Xmm result = ctx.reg_alloc.ScratchXmm();
|
||||
if (code.DoesCpuSupport(Xbyak::util::Cpu::tAVX)) {
|
||||
if (code.HasAVX()) {
|
||||
code.vpmulhw(result, x, y);
|
||||
} else {
|
||||
code.movdqa(result, x);
|
||||
|
|
@ -2962,7 +2962,7 @@ void EmitX64::EmitVectorSignedMultiply16(EmitContext& ctx, IR::Inst* inst) {
|
|||
|
||||
if (lower_inst) {
|
||||
const Xbyak::Xmm result = ctx.reg_alloc.ScratchXmm();
|
||||
if (code.DoesCpuSupport(Xbyak::util::Cpu::tAVX)) {
|
||||
if (code.HasAVX()) {
|
||||
code.vpmullw(result, x, y);
|
||||
} else {
|
||||
code.movdqa(result, x);
|
||||
|
|
@ -2979,7 +2979,7 @@ void EmitX64::EmitVectorSignedMultiply32(EmitContext& ctx, IR::Inst* inst) {
|
|||
|
||||
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
|
||||
|
||||
if (lower_inst && !upper_inst && code.DoesCpuSupport(Xbyak::util::Cpu::tAVX)) {
|
||||
if (lower_inst && !upper_inst && code.HasAVX()) {
|
||||
const Xbyak::Xmm x = ctx.reg_alloc.UseXmm(args[0]);
|
||||
const Xbyak::Xmm y = ctx.reg_alloc.UseXmm(args[1]);
|
||||
const Xbyak::Xmm result = ctx.reg_alloc.ScratchXmm();
|
||||
|
|
@ -2991,7 +2991,7 @@ void EmitX64::EmitVectorSignedMultiply32(EmitContext& ctx, IR::Inst* inst) {
|
|||
return;
|
||||
}
|
||||
|
||||
if (code.DoesCpuSupport(Xbyak::util::Cpu::tAVX)) {
|
||||
if (code.HasAVX()) {
|
||||
const Xbyak::Xmm x = ctx.reg_alloc.UseScratchXmm(args[0]);
|
||||
const Xbyak::Xmm y = ctx.reg_alloc.UseScratchXmm(args[1]);
|
||||
|
||||
|
|
@ -3148,7 +3148,7 @@ void EmitX64::EmitVectorSignedSaturatedAbs32(EmitContext& ctx, IR::Inst* inst) {
|
|||
}
|
||||
|
||||
void EmitX64::EmitVectorSignedSaturatedAbs64(EmitContext& ctx, IR::Inst* inst) {
|
||||
if (code.DoesCpuSupport(Xbyak::util::Cpu::tSSE41)) {
|
||||
if (code.HasSSE41()) {
|
||||
EmitVectorSignedSaturatedAbs(64, code, ctx, inst);
|
||||
return;
|
||||
}
|
||||
|
|
@ -3183,7 +3183,7 @@ static void EmitVectorSignedSaturatedAccumulateUnsigned(BlockOfCode& code, EmitC
|
|||
|
||||
switch (bit_width) {
|
||||
case 8:
|
||||
if (code.DoesCpuSupport(Xbyak::util::Cpu::tAVX)) {
|
||||
if (code.HasAVX()) {
|
||||
code.vpaddb(result, x, xmm0);
|
||||
} else {
|
||||
code.movdqa(result, x);
|
||||
|
|
@ -3191,7 +3191,7 @@ static void EmitVectorSignedSaturatedAccumulateUnsigned(BlockOfCode& code, EmitC
|
|||
}
|
||||
break;
|
||||
case 16:
|
||||
if (code.DoesCpuSupport(Xbyak::util::Cpu::tAVX)) {
|
||||
if (code.HasAVX()) {
|
||||
code.vpaddw(result, x, xmm0);
|
||||
} else {
|
||||
code.movdqa(result, x);
|
||||
|
|
@ -3199,7 +3199,7 @@ static void EmitVectorSignedSaturatedAccumulateUnsigned(BlockOfCode& code, EmitC
|
|||
}
|
||||
break;
|
||||
case 32:
|
||||
if (code.DoesCpuSupport(Xbyak::util::Cpu::tAVX)) {
|
||||
if (code.HasAVX()) {
|
||||
code.vpaddd(result, x, xmm0);
|
||||
} else {
|
||||
code.movdqa(result, x);
|
||||
|
|
@ -3207,7 +3207,7 @@ static void EmitVectorSignedSaturatedAccumulateUnsigned(BlockOfCode& code, EmitC
|
|||
}
|
||||
break;
|
||||
case 64:
|
||||
if (code.DoesCpuSupport(Xbyak::util::Cpu::tAVX)) {
|
||||
if (code.HasAVX()) {
|
||||
code.vpaddq(result, x, xmm0);
|
||||
} else {
|
||||
code.movdqa(result, x);
|
||||
|
|
@ -3216,10 +3216,10 @@ static void EmitVectorSignedSaturatedAccumulateUnsigned(BlockOfCode& code, EmitC
|
|||
break;
|
||||
}
|
||||
|
||||
if (code.DoesCpuSupport(Xbyak::util::Cpu::tAVX512VL)) {
|
||||
if (code.HasAVX512_Skylake()) {
|
||||
// xmm0 = majority(~y, x, res)
|
||||
code.vpternlogd(xmm0, x, result, 0b10001110);
|
||||
} else if (code.DoesCpuSupport(Xbyak::util::Cpu::tAVX)) {
|
||||
} else if (code.HasAVX()) {
|
||||
code.vpor(tmp, x, result);
|
||||
code.pand(x, result);
|
||||
code.vpblendvb(xmm0, tmp, x, xmm0);
|
||||
|
|
@ -3235,7 +3235,7 @@ static void EmitVectorSignedSaturatedAccumulateUnsigned(BlockOfCode& code, EmitC
|
|||
|
||||
switch (bit_width) {
|
||||
case 8:
|
||||
if (code.DoesCpuSupport(Xbyak::util::Cpu::tAVX)) {
|
||||
if (code.HasAVX()) {
|
||||
const Xbyak::Xmm tmp2 = ctx.reg_alloc.ScratchXmm();
|
||||
code.pcmpeqb(tmp2, tmp2);
|
||||
code.pxor(tmp, tmp);
|
||||
|
|
@ -3256,7 +3256,7 @@ static void EmitVectorSignedSaturatedAccumulateUnsigned(BlockOfCode& code, EmitC
|
|||
code.psrad(xmm0, 31);
|
||||
break;
|
||||
case 64:
|
||||
if (code.DoesCpuSupport(Xbyak::util::Cpu::tAVX512VL)) {
|
||||
if (code.HasAVX512_Skylake()) {
|
||||
code.vpsraq(xmm0, xmm0, 63);
|
||||
} else {
|
||||
code.psrad(xmm0, 31);
|
||||
|
|
@ -3286,7 +3286,7 @@ static void EmitVectorSignedSaturatedAccumulateUnsigned(BlockOfCode& code, EmitC
|
|||
code.pmovmskb(mask, xmm0);
|
||||
code.or_(code.dword[code.r15 + code.GetJitStateInfo().offsetof_fpsr_qc], mask);
|
||||
|
||||
if (code.DoesCpuSupport(Xbyak::util::Cpu::tSSE41)) {
|
||||
if (code.HasSSE41()) {
|
||||
code.pblendvb(result, tmp);
|
||||
} else {
|
||||
code.pandn(xmm0, result);
|
||||
|
|
@ -3323,14 +3323,14 @@ void EmitX64::EmitVectorSignedSaturatedDoublingMultiply16(EmitContext& ctx, IR::
|
|||
const Xbyak::Xmm upper_tmp = ctx.reg_alloc.ScratchXmm();
|
||||
const Xbyak::Xmm lower_tmp = ctx.reg_alloc.ScratchXmm();
|
||||
|
||||
if (code.DoesCpuSupport(Xbyak::util::Cpu::tAVX)) {
|
||||
if (code.HasAVX()) {
|
||||
code.vpmulhw(upper_tmp, x, y);
|
||||
} else {
|
||||
code.movdqa(upper_tmp, x);
|
||||
code.pmulhw(upper_tmp, y);
|
||||
}
|
||||
|
||||
if (code.DoesCpuSupport(Xbyak::util::Cpu::tAVX)) {
|
||||
if (code.HasAVX()) {
|
||||
code.vpmullw(lower_tmp, x, y);
|
||||
} else {
|
||||
code.movdqa(lower_tmp, x);
|
||||
|
|
@ -3343,7 +3343,7 @@ void EmitX64::EmitVectorSignedSaturatedDoublingMultiply16(EmitContext& ctx, IR::
|
|||
if (lower_inst) {
|
||||
const Xbyak::Xmm lower_result = ctx.reg_alloc.ScratchXmm();
|
||||
|
||||
if (code.DoesCpuSupport(Xbyak::util::Cpu::tAVX)) {
|
||||
if (code.HasAVX()) {
|
||||
code.vpaddw(lower_result, lower_tmp, lower_tmp);
|
||||
} else {
|
||||
code.movdqa(lower_result, lower_tmp);
|
||||
|
|
@ -3357,7 +3357,7 @@ void EmitX64::EmitVectorSignedSaturatedDoublingMultiply16(EmitContext& ctx, IR::
|
|||
if (upper_inst) {
|
||||
const Xbyak::Xmm upper_result = ctx.reg_alloc.ScratchXmm();
|
||||
|
||||
if (code.DoesCpuSupport(Xbyak::util::Cpu::tAVX)) {
|
||||
if (code.HasAVX()) {
|
||||
code.vpsrlw(lower_tmp, lower_tmp, 15);
|
||||
code.vpaddw(upper_tmp, upper_tmp, upper_tmp);
|
||||
code.vpor(upper_result, upper_tmp, lower_tmp);
|
||||
|
|
@ -3388,7 +3388,7 @@ void EmitX64::EmitVectorSignedSaturatedDoublingMultiply32(EmitContext& ctx, IR::
|
|||
|
||||
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
|
||||
|
||||
if (code.DoesCpuSupport(Xbyak::util::Cpu::tAVX)) {
|
||||
if (code.HasAVX()) {
|
||||
const Xbyak::Xmm x = ctx.reg_alloc.UseScratchXmm(args[0]);
|
||||
const Xbyak::Xmm y = ctx.reg_alloc.UseScratchXmm(args[1]);
|
||||
const Xbyak::Xmm odds = ctx.reg_alloc.ScratchXmm();
|
||||
|
|
@ -3508,7 +3508,7 @@ void EmitX64::EmitVectorSignedSaturatedDoublingMultiplyLong16(EmitContext& ctx,
|
|||
code.punpcklwd(y, y);
|
||||
code.pmaddwd(x, y);
|
||||
|
||||
if (code.DoesCpuSupport(Xbyak::util::Cpu::tAVX)) {
|
||||
if (code.HasAVX()) {
|
||||
code.vpcmpeqd(y, x, code.MConst(xword, 0x8000000080000000, 0x8000000080000000));
|
||||
code.vpxor(x, x, y);
|
||||
} else {
|
||||
|
|
@ -3530,7 +3530,7 @@ void EmitX64::EmitVectorSignedSaturatedDoublingMultiplyLong32(EmitContext& ctx,
|
|||
const Xbyak::Xmm x = ctx.reg_alloc.UseScratchXmm(args[0]);
|
||||
const Xbyak::Xmm y = ctx.reg_alloc.UseScratchXmm(args[1]);
|
||||
|
||||
if (code.DoesCpuSupport(Xbyak::util::Cpu::tAVX)) {
|
||||
if (code.HasAVX()) {
|
||||
code.vpmovsxdq(x, x);
|
||||
code.vpmovsxdq(y, y);
|
||||
code.vpmuldq(x, x, y);
|
||||
|
|
@ -3561,7 +3561,7 @@ void EmitX64::EmitVectorSignedSaturatedDoublingMultiplyLong32(EmitContext& ctx,
|
|||
}
|
||||
|
||||
const Xbyak::Reg32 bit = ctx.reg_alloc.ScratchGpr().cvt32();
|
||||
if (code.DoesCpuSupport(Xbyak::util::Cpu::tAVX)) {
|
||||
if (code.HasAVX()) {
|
||||
code.vpcmpeqq(y, x, code.MConst(xword, 0x8000000000000000, 0x8000000000000000));
|
||||
code.vpxor(x, x, y);
|
||||
code.vpmovmskb(bit, y);
|
||||
|
|
@ -3652,7 +3652,7 @@ static void EmitVectorSignedSaturatedNarrowToUnsigned(size_t original_esize, Blo
|
|||
code.punpcklbw(reconstructed, zero);
|
||||
break;
|
||||
case 32:
|
||||
ASSERT(code.DoesCpuSupport(Xbyak::util::Cpu::tSSE41));
|
||||
ASSERT(code.HasSSE41());
|
||||
code.packusdw(dest, dest); // SSE4.1
|
||||
code.movdqa(reconstructed, dest);
|
||||
code.punpcklwd(reconstructed, zero);
|
||||
|
|
@ -3675,7 +3675,7 @@ void EmitX64::EmitVectorSignedSaturatedNarrowToUnsigned16(EmitContext& ctx, IR::
|
|||
}
|
||||
|
||||
void EmitX64::EmitVectorSignedSaturatedNarrowToUnsigned32(EmitContext& ctx, IR::Inst* inst) {
|
||||
if (code.DoesCpuSupport(Xbyak::util::Cpu::tSSE41)) {
|
||||
if (code.HasSSE41()) {
|
||||
EmitVectorSignedSaturatedNarrowToUnsigned(32, code, ctx, inst);
|
||||
return;
|
||||
}
|
||||
|
|
@ -3784,7 +3784,7 @@ void EmitX64::EmitVectorSignedSaturatedNeg32(EmitContext& ctx, IR::Inst* inst) {
|
|||
}
|
||||
|
||||
void EmitX64::EmitVectorSignedSaturatedNeg64(EmitContext& ctx, IR::Inst* inst) {
|
||||
if (code.DoesCpuSupport(Xbyak::util::Cpu::tSSE41)) {
|
||||
if (code.HasSSE41()) {
|
||||
EmitVectorSignedSaturatedNeg(64, code, ctx, inst);
|
||||
return;
|
||||
}
|
||||
|
|
@ -3955,7 +3955,7 @@ void EmitX64::EmitVectorTableLookup(EmitContext& ctx, IR::Inst* inst) {
|
|||
|
||||
// TODO: AVX512VL implementation when available (VPERMB / VPERMI2B / VPERMT2B)
|
||||
|
||||
if (code.DoesCpuSupport(Xbyak::util::Cpu::tSSSE3) && is_defaults_zero && table_size == 1) {
|
||||
if (code.HasSSSE3() && is_defaults_zero && table_size == 1) {
|
||||
const Xbyak::Xmm indicies = ctx.reg_alloc.UseScratchXmm(args[2]);
|
||||
const Xbyak::Xmm xmm_table0 = ctx.reg_alloc.UseScratchXmm(table[0]);
|
||||
|
||||
|
|
@ -3966,12 +3966,12 @@ void EmitX64::EmitVectorTableLookup(EmitContext& ctx, IR::Inst* inst) {
|
|||
return;
|
||||
}
|
||||
|
||||
if (code.DoesCpuSupport(Xbyak::util::Cpu::tSSE41) && table_size == 1) {
|
||||
if (code.HasSSE41() && table_size == 1) {
|
||||
const Xbyak::Xmm indicies = ctx.reg_alloc.UseXmm(args[2]);
|
||||
const Xbyak::Xmm defaults = ctx.reg_alloc.UseXmm(args[0]);
|
||||
const Xbyak::Xmm xmm_table0 = ctx.reg_alloc.UseScratchXmm(table[0]);
|
||||
|
||||
if (code.DoesCpuSupport(Xbyak::util::Cpu::tAVX)) {
|
||||
if (code.HasAVX()) {
|
||||
code.vpaddusb(xmm0, indicies, code.MConst(xword, 0x7070707070707070, 0x7070707070707070));
|
||||
} else {
|
||||
code.movaps(xmm0, indicies);
|
||||
|
|
@ -3984,12 +3984,12 @@ void EmitX64::EmitVectorTableLookup(EmitContext& ctx, IR::Inst* inst) {
|
|||
return;
|
||||
}
|
||||
|
||||
if (code.DoesCpuSupport(Xbyak::util::Cpu::tSSE41) && is_defaults_zero && table_size == 2) {
|
||||
if (code.HasSSE41() && is_defaults_zero && table_size == 2) {
|
||||
const Xbyak::Xmm indicies = ctx.reg_alloc.UseScratchXmm(args[2]);
|
||||
const Xbyak::Xmm xmm_table0 = ctx.reg_alloc.UseScratchXmm(table[0]);
|
||||
const Xbyak::Xmm xmm_table1 = ctx.reg_alloc.UseScratchXmm(table[1]);
|
||||
|
||||
if (code.DoesCpuSupport(Xbyak::util::Cpu::tAVX)) {
|
||||
if (code.HasAVX()) {
|
||||
code.vpaddusb(xmm0, indicies, code.MConst(xword, 0x7070707070707070, 0x7070707070707070));
|
||||
} else {
|
||||
code.movaps(xmm0, indicies);
|
||||
|
|
@ -4004,7 +4004,7 @@ void EmitX64::EmitVectorTableLookup(EmitContext& ctx, IR::Inst* inst) {
|
|||
return;
|
||||
}
|
||||
|
||||
if (code.DoesCpuSupport(Xbyak::util::Cpu::tSSE41)) {
|
||||
if (code.HasSSE41()) {
|
||||
const Xbyak::Xmm indicies = ctx.reg_alloc.UseXmm(args[2]);
|
||||
const Xbyak::Xmm result = ctx.reg_alloc.UseScratchXmm(args[0]);
|
||||
const Xbyak::Xmm masked = ctx.reg_alloc.ScratchXmm();
|
||||
|
|
@ -4020,7 +4020,7 @@ void EmitX64::EmitVectorTableLookup(EmitContext& ctx, IR::Inst* inst) {
|
|||
if (table_index == 0) {
|
||||
code.pxor(xmm0, xmm0);
|
||||
code.pcmpeqb(xmm0, masked);
|
||||
} else if (code.DoesCpuSupport(Xbyak::util::Cpu::tAVX)) {
|
||||
} else if (code.HasAVX()) {
|
||||
code.vpcmpeqb(xmm0, masked, code.MConst(xword, table_index, table_index));
|
||||
} else {
|
||||
code.movaps(xmm0, code.MConst(xword, table_index, table_index));
|
||||
|
|
@ -4101,7 +4101,7 @@ static void EmitVectorUnsignedAbsoluteDifference(size_t esize, EmitContext& ctx,
|
|||
break;
|
||||
}
|
||||
case 32:
|
||||
if (code.DoesCpuSupport(Xbyak::util::Cpu::tSSE41)) {
|
||||
if (code.HasSSE41()) {
|
||||
const Xbyak::Xmm x = ctx.reg_alloc.UseScratchXmm(args[0]);
|
||||
const Xbyak::Xmm y = ctx.reg_alloc.UseXmm(args[1]);
|
||||
|
||||
|
|
@ -4151,7 +4151,7 @@ void EmitX64::EmitVectorUnsignedMultiply16(EmitContext& ctx, IR::Inst* inst) {
|
|||
|
||||
if (upper_inst) {
|
||||
const Xbyak::Xmm result = ctx.reg_alloc.ScratchXmm();
|
||||
if (code.DoesCpuSupport(Xbyak::util::Cpu::tAVX)) {
|
||||
if (code.HasAVX()) {
|
||||
code.vpmulhuw(result, x, y);
|
||||
} else {
|
||||
code.movdqa(result, x);
|
||||
|
|
@ -4164,7 +4164,7 @@ void EmitX64::EmitVectorUnsignedMultiply16(EmitContext& ctx, IR::Inst* inst) {
|
|||
|
||||
if (lower_inst) {
|
||||
const Xbyak::Xmm result = ctx.reg_alloc.ScratchXmm();
|
||||
if (code.DoesCpuSupport(Xbyak::util::Cpu::tAVX)) {
|
||||
if (code.HasAVX()) {
|
||||
code.vpmullw(result, x, y);
|
||||
} else {
|
||||
code.movdqa(result, x);
|
||||
|
|
@ -4181,7 +4181,7 @@ void EmitX64::EmitVectorUnsignedMultiply32(EmitContext& ctx, IR::Inst* inst) {
|
|||
|
||||
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
|
||||
|
||||
if (lower_inst && !upper_inst && code.DoesCpuSupport(Xbyak::util::Cpu::tAVX)) {
|
||||
if (lower_inst && !upper_inst && code.HasAVX()) {
|
||||
const Xbyak::Xmm x = ctx.reg_alloc.UseXmm(args[0]);
|
||||
const Xbyak::Xmm y = ctx.reg_alloc.UseXmm(args[1]);
|
||||
const Xbyak::Xmm result = ctx.reg_alloc.ScratchXmm();
|
||||
|
|
@ -4193,7 +4193,7 @@ void EmitX64::EmitVectorUnsignedMultiply32(EmitContext& ctx, IR::Inst* inst) {
|
|||
return;
|
||||
}
|
||||
|
||||
if (code.DoesCpuSupport(Xbyak::util::Cpu::tAVX)) {
|
||||
if (code.HasAVX()) {
|
||||
const Xbyak::Xmm x = ctx.reg_alloc.UseScratchXmm(args[0]);
|
||||
const Xbyak::Xmm y = ctx.reg_alloc.UseScratchXmm(args[1]);
|
||||
|
||||
|
|
@ -4442,7 +4442,7 @@ void EmitX64::EmitVectorUnsignedSaturatedShiftLeft64(EmitContext& ctx, IR::Inst*
|
|||
void EmitX64::EmitVectorZeroExtend8(EmitContext& ctx, IR::Inst* inst) {
|
||||
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
|
||||
const Xbyak::Xmm a = ctx.reg_alloc.UseScratchXmm(args[0]);
|
||||
if (code.DoesCpuSupport(Xbyak::util::Cpu::tSSE41)) {
|
||||
if (code.HasSSE41()) {
|
||||
code.pmovzxbw(a, a);
|
||||
} else {
|
||||
const Xbyak::Xmm zeros = ctx.reg_alloc.ScratchXmm();
|
||||
|
|
@ -4455,7 +4455,7 @@ void EmitX64::EmitVectorZeroExtend8(EmitContext& ctx, IR::Inst* inst) {
|
|||
void EmitX64::EmitVectorZeroExtend16(EmitContext& ctx, IR::Inst* inst) {
|
||||
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
|
||||
const Xbyak::Xmm a = ctx.reg_alloc.UseScratchXmm(args[0]);
|
||||
if (code.DoesCpuSupport(Xbyak::util::Cpu::tSSE41)) {
|
||||
if (code.HasSSE41()) {
|
||||
code.pmovzxwd(a, a);
|
||||
} else {
|
||||
const Xbyak::Xmm zeros = ctx.reg_alloc.ScratchXmm();
|
||||
|
|
@ -4468,7 +4468,7 @@ void EmitX64::EmitVectorZeroExtend16(EmitContext& ctx, IR::Inst* inst) {
|
|||
void EmitX64::EmitVectorZeroExtend32(EmitContext& ctx, IR::Inst* inst) {
|
||||
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
|
||||
const Xbyak::Xmm a = ctx.reg_alloc.UseScratchXmm(args[0]);
|
||||
if (code.DoesCpuSupport(Xbyak::util::Cpu::tSSE41)) {
|
||||
if (code.HasSSE41()) {
|
||||
code.pmovzxdq(a, a);
|
||||
} else {
|
||||
const Xbyak::Xmm zeros = ctx.reg_alloc.ScratchXmm();
|
||||
|
|
|
|||
|
|
@ -82,7 +82,7 @@ template<size_t fsize, size_t nargs, typename NaNHandler>
|
|||
void HandleNaNs(BlockOfCode& code, EmitContext& ctx, std::array<Xbyak::Xmm, nargs + 1> xmms, const Xbyak::Xmm& nan_mask, NaNHandler nan_handler) {
|
||||
static_assert(fsize == 32 || fsize == 64, "fsize must be either 32 or 64");
|
||||
|
||||
if (code.DoesCpuSupport(Xbyak::util::Cpu::tSSE41)) {
|
||||
if (code.HasSSE41()) {
|
||||
code.ptest(nan_mask, nan_mask);
|
||||
} else {
|
||||
const Xbyak::Reg32 bitmask = ctx.reg_alloc.ScratchGpr().cvt32();
|
||||
|
|
@ -169,7 +169,7 @@ template<size_t fsize>
|
|||
void ForceToDefaultNaN(BlockOfCode& code, EmitContext& ctx, Xbyak::Xmm result) {
|
||||
if (ctx.FPCR().DN()) {
|
||||
const Xbyak::Xmm nan_mask = xmm0;
|
||||
if (code.DoesCpuSupport(Xbyak::util::Cpu::tAVX)) {
|
||||
if (code.HasAVX()) {
|
||||
FCODE(vcmpunordp)(nan_mask, result, result);
|
||||
FCODE(blendvp)(result, GetNaNVector<fsize>(code));
|
||||
} else {
|
||||
|
|
@ -185,7 +185,7 @@ void ForceToDefaultNaN(BlockOfCode& code, EmitContext& ctx, Xbyak::Xmm result) {
|
|||
template<size_t fsize>
|
||||
void ZeroIfNaN(BlockOfCode& code, Xbyak::Xmm result) {
|
||||
const Xbyak::Xmm nan_mask = xmm0;
|
||||
if (code.DoesCpuSupport(Xbyak::util::Cpu::tAVX)) {
|
||||
if (code.HasAVX()) {
|
||||
FCODE(vcmpordp)(nan_mask, result, result);
|
||||
FCODE(vandp)(result, result, nan_mask);
|
||||
} else {
|
||||
|
|
@ -301,7 +301,7 @@ void EmitTwoOpVectorOperation(BlockOfCode& code, EmitContext& ctx, IR::Inst* ins
|
|||
fn(result, xmm_a);
|
||||
}
|
||||
|
||||
if (code.DoesCpuSupport(Xbyak::util::Cpu::tAVX)) {
|
||||
if (code.HasAVX()) {
|
||||
FCODE(vcmpunordp)(nan_mask, result, result);
|
||||
} else {
|
||||
code.movaps(nan_mask, result);
|
||||
|
|
@ -588,9 +588,9 @@ void EmitX64::EmitFPVectorFromSignedFixed64(EmitContext& ctx, IR::Inst* inst) {
|
|||
const FP::RoundingMode rounding_mode = static_cast<FP::RoundingMode>(args[2].GetImmediateU8());
|
||||
ASSERT(rounding_mode == ctx.FPCR().RMode());
|
||||
|
||||
if (code.DoesCpuSupport(Xbyak::util::Cpu::tAVX512VL) && code.DoesCpuSupport(Xbyak::util::Cpu::tAVX512DQ)) {
|
||||
if (code.HasAVX512_Skylake()) {
|
||||
code.vcvtqq2pd(xmm, xmm);
|
||||
} else if (code.DoesCpuSupport(Xbyak::util::Cpu::tSSE41)) {
|
||||
} else if (code.HasSSE41()) {
|
||||
const Xbyak::Xmm xmm_tmp = ctx.reg_alloc.ScratchXmm();
|
||||
const Xbyak::Reg64 tmp = ctx.reg_alloc.ScratchGpr();
|
||||
|
||||
|
|
@ -636,7 +636,7 @@ void EmitX64::EmitFPVectorFromUnsignedFixed32(EmitContext& ctx, IR::Inst* inst)
|
|||
const FP::RoundingMode rounding_mode = static_cast<FP::RoundingMode>(args[2].GetImmediateU8());
|
||||
ASSERT(rounding_mode == ctx.FPCR().RMode());
|
||||
|
||||
if (code.DoesCpuSupport(Xbyak::util::Cpu::tAVX512DQ) && code.DoesCpuSupport(Xbyak::util::Cpu::tAVX512VL)) {
|
||||
if (code.HasAVX512_Skylake()) {
|
||||
code.vcvtudq2ps(xmm, xmm);
|
||||
} else {
|
||||
const Xbyak::Address mem_4B000000 = code.MConst(xword, 0x4B0000004B000000, 0x4B0000004B000000);
|
||||
|
|
@ -645,7 +645,7 @@ void EmitX64::EmitFPVectorFromUnsignedFixed32(EmitContext& ctx, IR::Inst* inst)
|
|||
|
||||
const Xbyak::Xmm tmp = ctx.reg_alloc.ScratchXmm();
|
||||
|
||||
if (code.DoesCpuSupport(Xbyak::util::Cpu::tAVX)) {
|
||||
if (code.HasAVX()) {
|
||||
code.vpblendw(tmp, xmm, mem_4B000000, 0b10101010);
|
||||
code.vpsrld(xmm, xmm, 16);
|
||||
code.vpblendw(xmm, xmm, mem_53000000, 0b10101010);
|
||||
|
|
@ -683,7 +683,7 @@ void EmitX64::EmitFPVectorFromUnsignedFixed64(EmitContext& ctx, IR::Inst* inst)
|
|||
const FP::RoundingMode rounding_mode = static_cast<FP::RoundingMode>(args[2].GetImmediateU8());
|
||||
ASSERT(rounding_mode == ctx.FPCR().RMode());
|
||||
|
||||
if (code.DoesCpuSupport(Xbyak::util::Cpu::tAVX512DQ) && code.DoesCpuSupport(Xbyak::util::Cpu::tAVX512VL)) {
|
||||
if (code.HasAVX512_Skylake()) {
|
||||
code.vcvtuqq2pd(xmm, xmm);
|
||||
} else {
|
||||
const Xbyak::Address unpack = code.MConst(xword, 0x4530000043300000, 0);
|
||||
|
|
@ -693,7 +693,7 @@ void EmitX64::EmitFPVectorFromUnsignedFixed64(EmitContext& ctx, IR::Inst* inst)
|
|||
const Xbyak::Xmm subtrahend_reg = ctx.reg_alloc.ScratchXmm();
|
||||
const Xbyak::Xmm tmp1 = ctx.reg_alloc.ScratchXmm();
|
||||
|
||||
if (code.DoesCpuSupport(Xbyak::util::Cpu::tAVX)) {
|
||||
if (code.HasAVX()) {
|
||||
code.vmovapd(unpack_reg, unpack);
|
||||
code.vmovapd(subtrahend_reg, subtrahend);
|
||||
|
||||
|
|
@ -793,7 +793,7 @@ static void EmitFPVectorMinMax(BlockOfCode& code, EmitContext& ctx, IR::Inst* in
|
|||
|
||||
DenormalsAreZero<fsize>(code, ctx, {result, xmm_b}, mask);
|
||||
|
||||
if (code.DoesCpuSupport(Xbyak::util::Cpu::tAVX)) {
|
||||
if (code.HasAVX()) {
|
||||
FCODE(vcmpeqp)(mask, result, xmm_b);
|
||||
FCODE(vcmpunordp)(nan_mask, result, xmm_b);
|
||||
if constexpr (is_max) {
|
||||
|
|
@ -849,7 +849,7 @@ static void EmitFPVectorMinMax(BlockOfCode& code, EmitContext& ctx, IR::Inst* in
|
|||
// x86-64 treats differently signed zeros as equal while ARM does not.
|
||||
// Thus if we AND together things that x86-64 thinks are equal we'll get the positive zero.
|
||||
|
||||
if (code.DoesCpuSupport(Xbyak::util::Cpu::tAVX)) {
|
||||
if (code.HasAVX()) {
|
||||
FCODE(vcmpeqp)(mask, result, xmm_b);
|
||||
if constexpr (is_max) {
|
||||
FCODE(vandp)(eq, result, xmm_b);
|
||||
|
|
@ -914,7 +914,7 @@ void EmitFPVectorMulAdd(BlockOfCode& code, EmitContext& ctx, IR::Inst* inst) {
|
|||
};
|
||||
|
||||
if constexpr (fsize != 16) {
|
||||
if (code.DoesCpuSupport(Xbyak::util::Cpu::tFMA) && code.DoesCpuSupport(Xbyak::util::Cpu::tAVX)) {
|
||||
if (code.HasFMA() && code.HasAVX()) {
|
||||
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
|
||||
|
||||
const Xbyak::Xmm result = ctx.reg_alloc.ScratchXmm();
|
||||
|
|
@ -971,7 +971,7 @@ static void EmitFPVectorMulX(BlockOfCode& code, EmitContext& ctx, IR::Inst* inst
|
|||
|
||||
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
|
||||
|
||||
if (ctx.FPCR().DN() && code.DoesCpuSupport(Xbyak::util::Cpu::tAVX)) {
|
||||
if (ctx.FPCR().DN() && code.HasAVX()) {
|
||||
const Xbyak::Xmm result = ctx.reg_alloc.UseScratchXmm(args[0]);
|
||||
const Xbyak::Xmm operand = ctx.reg_alloc.UseXmm(args[1]);
|
||||
const Xbyak::Xmm tmp = ctx.reg_alloc.ScratchXmm();
|
||||
|
|
@ -1120,7 +1120,7 @@ static void EmitRecipStepFused(BlockOfCode& code, EmitContext& ctx, IR::Inst* in
|
|||
};
|
||||
|
||||
if constexpr (fsize != 16) {
|
||||
if (code.DoesCpuSupport(Xbyak::util::Cpu::tFMA) && code.DoesCpuSupport(Xbyak::util::Cpu::tAVX)) {
|
||||
if (code.HasFMA() && code.HasAVX()) {
|
||||
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
|
||||
|
||||
const Xbyak::Xmm result = ctx.reg_alloc.ScratchXmm();
|
||||
|
|
@ -1176,7 +1176,7 @@ void EmitFPVectorRoundInt(BlockOfCode& code, EmitContext& ctx, IR::Inst* inst) {
|
|||
const bool exact = inst->GetArg(2).GetU1();
|
||||
|
||||
if constexpr (fsize != 16) {
|
||||
if (code.DoesCpuSupport(Xbyak::util::Cpu::tSSE41) && rounding != FP::RoundingMode::ToNearest_TieAwayFromZero && !exact) {
|
||||
if (code.HasSSE41() && rounding != FP::RoundingMode::ToNearest_TieAwayFromZero && !exact) {
|
||||
const u8 round_imm = [&]() -> u8 {
|
||||
switch (rounding) {
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||||
case FP::RoundingMode::ToNearest_TieEven:
|
||||
|
|
@ -1276,7 +1276,7 @@ static void EmitRSqrtStepFused(BlockOfCode& code, EmitContext& ctx, IR::Inst* in
|
|||
};
|
||||
|
||||
if constexpr (fsize != 16) {
|
||||
if (code.DoesCpuSupport(Xbyak::util::Cpu::tFMA) && code.DoesCpuSupport(Xbyak::util::Cpu::tAVX)) {
|
||||
if (code.HasFMA() && code.HasAVX()) {
|
||||
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
|
||||
|
||||
const Xbyak::Xmm result = ctx.reg_alloc.ScratchXmm();
|
||||
|
|
@ -1364,7 +1364,7 @@ void EmitFPVectorToFixed(BlockOfCode& code, EmitContext& ctx, IR::Inst* inst) {
|
|||
// TODO: AVX512 implementation
|
||||
|
||||
if constexpr (fsize != 16) {
|
||||
if (code.DoesCpuSupport(Xbyak::util::Cpu::tSSE41) && rounding != FP::RoundingMode::ToNearest_TieAwayFromZero) {
|
||||
if (code.HasSSE41() && rounding != FP::RoundingMode::ToNearest_TieAwayFromZero) {
|
||||
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
|
||||
|
||||
const Xbyak::Xmm src = ctx.reg_alloc.UseScratchXmm(args[0]);
|
||||
|
|
|
|||
|
|
@ -28,7 +28,7 @@ void EmitVectorSaturatedNative(BlockOfCode& code, EmitContext& ctx, IR::Inst* in
|
|||
|
||||
(code.*unsaturated_fn)(xmm0, addend);
|
||||
(code.*sub_fn)(xmm0, result);
|
||||
if (code.DoesCpuSupport(Xbyak::util::Cpu::tSSE41)) {
|
||||
if (code.HasSSE41()) {
|
||||
code.ptest(xmm0, xmm0);
|
||||
} else {
|
||||
const Xbyak::Xmm tmp = ctx.reg_alloc.ScratchXmm();
|
||||
|
|
@ -96,7 +96,7 @@ void EmitVectorSignedSaturated(BlockOfCode& code, EmitContext& ctx, IR::Inst* in
|
|||
}
|
||||
code.pxor(tmp, code.MConst(xword, msb_mask, msb_mask));
|
||||
|
||||
if (code.DoesCpuSupport(Xbyak::util::Cpu::tSSE41)) {
|
||||
if (code.HasSSE41()) {
|
||||
code.ptest(xmm0, code.MConst(xword, msb_mask, msb_mask));
|
||||
} else {
|
||||
if constexpr (esize == 32) {
|
||||
|
|
@ -109,7 +109,7 @@ void EmitVectorSignedSaturated(BlockOfCode& code, EmitContext& ctx, IR::Inst* in
|
|||
code.setnz(overflow);
|
||||
code.or_(code.byte[code.r15 + code.GetJitStateInfo().offsetof_fpsr_qc], overflow);
|
||||
|
||||
if (code.DoesCpuSupport(Xbyak::util::Cpu::tSSE41)) {
|
||||
if (code.HasSSE41()) {
|
||||
if constexpr (esize == 32) {
|
||||
code.blendvps(result, tmp);
|
||||
} else {
|
||||
|
|
@ -196,7 +196,7 @@ void EmitX64::EmitVectorUnsignedSaturatedAdd32(EmitContext& ctx, IR::Inst* inst)
|
|||
|
||||
code.por(result, tmp);
|
||||
|
||||
if (code.DoesCpuSupport(Xbyak::util::Cpu::tSSE41)) {
|
||||
if (code.HasSSE41()) {
|
||||
code.ptest(tmp, tmp);
|
||||
} else {
|
||||
code.movmskps(overflow.cvt32(), tmp);
|
||||
|
|
@ -232,7 +232,7 @@ void EmitX64::EmitVectorUnsignedSaturatedAdd64(EmitContext& ctx, IR::Inst* inst)
|
|||
|
||||
code.por(result, tmp);
|
||||
|
||||
if (code.DoesCpuSupport(Xbyak::util::Cpu::tSSE41)) {
|
||||
if (code.HasSSE41()) {
|
||||
code.ptest(tmp, tmp);
|
||||
} else {
|
||||
code.movmskpd(overflow.cvt32(), tmp);
|
||||
|
|
@ -273,7 +273,7 @@ void EmitX64::EmitVectorUnsignedSaturatedSub32(EmitContext& ctx, IR::Inst* inst)
|
|||
code.psubd(tmp, xmm0);
|
||||
code.psrad(tmp, 31);
|
||||
|
||||
if (code.DoesCpuSupport(Xbyak::util::Cpu::tSSE41)) {
|
||||
if (code.HasSSE41()) {
|
||||
code.ptest(tmp, tmp);
|
||||
} else {
|
||||
code.movmskps(overflow.cvt32(), tmp);
|
||||
|
|
@ -308,7 +308,7 @@ void EmitX64::EmitVectorUnsignedSaturatedSub64(EmitContext& ctx, IR::Inst* inst)
|
|||
code.psrad(tmp, 31);
|
||||
code.pshufd(tmp, tmp, 0b11110101);
|
||||
|
||||
if (code.DoesCpuSupport(Xbyak::util::Cpu::tSSE41)) {
|
||||
if (code.HasSSE41()) {
|
||||
code.ptest(tmp, tmp);
|
||||
} else {
|
||||
code.movmskpd(overflow.cvt32(), tmp);
|
||||
|
|
|
|||
|
|
@ -18,7 +18,7 @@ namespace Dynarmic::Backend::X64 {
|
|||
|
||||
#define MAYBE_AVX(OPCODE, ...) \
|
||||
[&] { \
|
||||
if (code.DoesCpuSupport(Xbyak::util::Cpu::tAVX)) { \
|
||||
if (code.HasAVX()) { \
|
||||
code.v##OPCODE(__VA_ARGS__); \
|
||||
} else { \
|
||||
code.OPCODE(__VA_ARGS__); \
|
||||
|
|
|
|||
Loading…
Reference in a new issue