Merge pull request #582 from lioncash/pbi
thumb32: Implement most plain binary immediate instructions
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f09e400858
4 changed files with 217 additions and 12 deletions
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@ -72,21 +72,20 @@ INST(thumb32_RSB_imm, "RSB (imm)", "11110v01110Snnnn0vvvdd
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// Data Processing (Plain Binary Immediate)
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//INST(thumb32_ADR, "ADR", "11110-10000011110---------------")
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//INST(thumb32_ADD_imm_2, "ADD (imm)", "11110-100000----0---------------")
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INST(thumb32_ADD_imm_2, "ADD (imm)", "11110i10000011010iiiddddiiiiiiii")
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INST(thumb32_MOVW_imm, "MOVW (imm)", "11110i100100iiii0iiiddddiiiiiiii")
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//INST(thumb32_ADR, "ADR", "11110-10101011110---------------")
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//INST(thumb32_SUB_imm_2, "SUB (imm)", "11110-101010----0---------------")
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INST(thumb32_SUB_imm_2, "SUB (imm)", "11110i10101011010iiiddddiiiiiiii")
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INST(thumb32_MOVT, "MOVT", "11110i101100iiii0iiiddddiiiiiiii")
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//INST(thumb32_SSAT, "SSAT", "11110-110000----0---------------")
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//INST(thumb32_SSAT16, "SSAT16", "11110-110010----0000----00------")
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//INST(thumb32_SSAT, "SSAT", "11110-110010----0---------------")
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//INST(thumb32_SBFX, "SBFX", "11110-110100----0---------------")
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//INST(thumb32_BFC, "BFC", "11110-11011011110---------------")
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//INST(thumb32_BFI, "BFI", "11110-110110----0---------------")
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//INST(thumb32_USAT, "USAT", "11110-111000----0---------------")
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//INST(thumb32_USAT16, "USAT16", "11110-111010----0000----00------")
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//INST(thumb32_USAT, "USAT", "11110-111010----0---------------")
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//INST(thumb32_UBFX, "UBFX", "11110-111100----0---------------")
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INST(thumb32_UDF, "Invalid decoding", "11110011-010----0000----0001----")
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INST(thumb32_SSAT16, "SSAT16", "111100110010nnnn0000dddd0000iiii")
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INST(thumb32_USAT16, "USAT16", "111100111010nnnn0000dddd0000iiii")
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INST(thumb32_SSAT, "SSAT", "1111001100s0nnnn0iiiddddii0bbbbb")
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INST(thumb32_USAT, "USAT", "1111001110s0nnnn0iiiddddii0bbbbb")
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INST(thumb32_SBFX, "SBFX", "111100110100nnnn0iiiddddii0wwwww")
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INST(thumb32_BFC, "BFC", "11110011011011110iiiddddii0bbbbb")
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INST(thumb32_BFI, "BFI", "111100110110nnnn0iiiddddii0bbbbb")
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INST(thumb32_UBFX, "UBFX", "111100111100nnnn0iiiddddii0wwwww")
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// Branches and Miscellaneous Control
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//INST(thumb32_MSR_banked, "MSR (banked)", "11110011100-----10-0------1-----")
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@ -3,9 +3,109 @@
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* SPDX-License-Identifier: 0BSD
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*/
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#include "common/assert.h"
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#include "common/bit_util.h"
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#include "frontend/A32/translate/impl/translate_thumb.h"
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namespace Dynarmic::A32 {
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static IR::U32 Pack2x16To1x32(A32::IREmitter& ir, IR::U32 lo, IR::U32 hi) {
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return ir.Or(ir.And(lo, ir.Imm32(0xFFFF)), ir.LogicalShiftLeft(hi, ir.Imm8(16), ir.Imm1(0)).result);
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}
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static IR::U16 MostSignificantHalf(A32::IREmitter& ir, IR::U32 value) {
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return ir.LeastSignificantHalf(ir.LogicalShiftRight(value, ir.Imm8(16), ir.Imm1(0)).result);
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}
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using SaturationFunction = IR::ResultAndOverflow<IR::U32> (IREmitter::*)(const IR::U32&, size_t);
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static bool Saturation(ThumbTranslatorVisitor& v, bool sh, Reg n, Reg d, Imm<5> shift_amount, size_t saturate_to, SaturationFunction sat_fn) {
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ASSERT_MSG(!(sh && shift_amount == 0), "Invalid decode");
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if (d == Reg::PC || n == Reg::PC) {
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return v.UnpredictableInstruction();
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}
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const auto shift = sh ? ShiftType::ASR : ShiftType::LSL;
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const auto operand = v.EmitImmShift(v.ir.GetRegister(n), shift, shift_amount, v.ir.GetCFlag());
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const auto result = (v.ir.*sat_fn)(operand.result, saturate_to);
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v.ir.SetRegister(d, result.result);
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v.ir.OrQFlag(result.overflow);
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return true;
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}
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static bool Saturation16(ThumbTranslatorVisitor& v, Reg n, Reg d, size_t saturate_to, SaturationFunction sat_fn) {
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if (d == Reg::PC || n == Reg::PC) {
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return v.UnpredictableInstruction();
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}
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const auto reg_n = v.ir.GetRegister(n);
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const auto lo_operand = v.ir.SignExtendHalfToWord(v.ir.LeastSignificantHalf(reg_n));
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const auto hi_operand = v.ir.SignExtendHalfToWord(MostSignificantHalf(v.ir, reg_n));
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const auto lo_result = (v.ir.*sat_fn)(lo_operand, saturate_to);
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const auto hi_result = (v.ir.*sat_fn)(hi_operand, saturate_to);
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v.ir.SetRegister(d, Pack2x16To1x32(v.ir, lo_result.result, hi_result.result));
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v.ir.OrQFlag(lo_result.overflow);
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v.ir.OrQFlag(hi_result.overflow);
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return true;
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}
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bool ThumbTranslatorVisitor::thumb32_ADD_imm_2(Imm<1> imm1, Imm<3> imm3, Reg d, Imm<8> imm8) {
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if (d == Reg::PC) {
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return UnpredictableInstruction();
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}
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const u32 imm = concatenate(imm1, imm3, imm8).ZeroExtend();
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const auto sp = ir.GetRegister(Reg::SP);
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const auto result = ir.AddWithCarry(sp, ir.Imm32(imm), ir.Imm1(0));
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ir.SetRegister(d, result.result);
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return true;
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}
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bool ThumbTranslatorVisitor::thumb32_BFC(Imm<3> imm3, Reg d, Imm<2> imm2, Imm<5> msb) {
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if (d == Reg::PC) {
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return UnpredictableInstruction();
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}
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const u32 lsbit = concatenate(imm3, imm2).ZeroExtend();
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const u32 msbit = msb.ZeroExtend();
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if (msbit < lsbit) {
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return UnpredictableInstruction();
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}
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const u32 mask = ~(Common::Ones<u32>(msbit - lsbit + 1) << lsbit);
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const auto reg_d = ir.GetRegister(d);
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const auto result = ir.And(reg_d, ir.Imm32(mask));
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ir.SetRegister(d, result);
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return true;
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}
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bool ThumbTranslatorVisitor::thumb32_BFI(Reg n, Imm<3> imm3, Reg d, Imm<2> imm2, Imm<5> msb) {
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if (d == Reg::PC || n == Reg::PC) {
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return UnpredictableInstruction();
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}
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const u32 lsbit = concatenate(imm3, imm2).ZeroExtend();
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const u32 msbit = msb.ZeroExtend();
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if (msbit < lsbit) {
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return UnpredictableInstruction();
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}
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const u32 inclusion_mask = Common::Ones<u32>(msbit - lsbit + 1) << lsbit;
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const u32 exclusion_mask = ~inclusion_mask;
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const IR::U32 operand1 = ir.And(ir.GetRegister(d), ir.Imm32(exclusion_mask));
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const IR::U32 operand2 = ir.And(ir.LogicalShiftLeft(ir.GetRegister(n), ir.Imm8(u8(lsbit))), ir.Imm32(inclusion_mask));
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const IR::U32 result = ir.Or(operand1, operand2);
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ir.SetRegister(d, result);
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return true;
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}
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bool ThumbTranslatorVisitor::thumb32_MOVT(Imm<1> imm1, Imm<4> imm4, Imm<3> imm3, Reg d, Imm<8> imm8) {
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if (d == Reg::PC) {
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@ -31,4 +131,77 @@ bool ThumbTranslatorVisitor::thumb32_MOVW_imm(Imm<1> imm1, Imm<4> imm4, Imm<3> i
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return true;
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}
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bool ThumbTranslatorVisitor::thumb32_SBFX(Reg n, Imm<3> imm3, Reg d, Imm<2> imm2, Imm<5> widthm1) {
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if (d == Reg::PC || n == Reg::PC) {
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return UnpredictableInstruction();
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}
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const u32 lsbit = concatenate(imm3, imm2).ZeroExtend();
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const u32 widthm1_value = widthm1.ZeroExtend();
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const u32 msb = lsbit + widthm1_value;
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if (msb >= Common::BitSize<u32>()) {
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return UnpredictableInstruction();
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}
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constexpr size_t max_width = Common::BitSize<u32>();
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const auto width = widthm1_value + 1;
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const auto left_shift_amount = static_cast<u8>(max_width - width - lsbit);
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const auto right_shift_amount = static_cast<u8>(max_width - width);
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const auto operand = ir.GetRegister(n);
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const auto tmp = ir.LogicalShiftLeft(operand, ir.Imm8(left_shift_amount));
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const auto result = ir.ArithmeticShiftRight(tmp, ir.Imm8(right_shift_amount));
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ir.SetRegister(d, result);
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return true;
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}
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bool ThumbTranslatorVisitor::thumb32_SSAT(bool sh, Reg n, Imm<3> imm3, Reg d, Imm<2> imm2, Imm<5> sat_imm) {
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return Saturation(*this, sh, n, d, concatenate(imm3, imm2), sat_imm.ZeroExtend() + 1, &IREmitter::SignedSaturation);
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}
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bool ThumbTranslatorVisitor::thumb32_SSAT16(Reg n, Reg d, Imm<4> sat_imm) {
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return Saturation16(*this, n, d, sat_imm.ZeroExtend() + 1, &IREmitter::SignedSaturation);
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}
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bool ThumbTranslatorVisitor::thumb32_SUB_imm_2(Imm<1> imm1, Imm<3> imm3, Reg d, Imm<8> imm8) {
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if (d == Reg::PC) {
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return UnpredictableInstruction();
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}
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const u32 imm = concatenate(imm1, imm3, imm8).ZeroExtend();
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const auto sp = ir.GetRegister(Reg::SP);
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const auto result = ir.SubWithCarry(sp, ir.Imm32(imm), ir.Imm1(1));
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ir.SetRegister(d, result.result);
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return true;
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}
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bool ThumbTranslatorVisitor::thumb32_UBFX(Reg n, Imm<3> imm3, Reg d, Imm<2> imm2, Imm<5> widthm1) {
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if (d == Reg::PC || n == Reg::PC) {
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return UnpredictableInstruction();
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}
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const u32 lsbit = concatenate(imm3, imm2).ZeroExtend();
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const u32 widthm1_value = widthm1.ZeroExtend();
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const u32 msb = lsbit + widthm1_value;
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if (msb >= Common::BitSize<u32>()) {
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return UnpredictableInstruction();
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}
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const auto operand = ir.GetRegister(n);
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const auto mask = ir.Imm32(Common::Ones<u32>(widthm1_value + 1));
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const auto result = ir.And(ir.LogicalShiftRight(operand, ir.Imm8(u8(lsbit))), mask);
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ir.SetRegister(d, result);
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return true;
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}
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bool ThumbTranslatorVisitor::thumb32_USAT(bool sh, Reg n, Imm<3> imm3, Reg d, Imm<2> imm2, Imm<5> sat_imm) {
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return Saturation(*this, sh, n, d, concatenate(imm3, imm2), sat_imm.ZeroExtend(), &IREmitter::UnsignedSaturation);
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}
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bool ThumbTranslatorVisitor::thumb32_USAT16(Reg n, Reg d, Imm<4> sat_imm) {
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return Saturation16(*this, n, d, sat_imm.ZeroExtend(), &IREmitter::UnsignedSaturation);
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}
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} // namespace Dynarmic::A32
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@ -67,6 +67,8 @@ struct ThumbTranslatorVisitor final {
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bool UndefinedInstruction();
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bool RaiseException(Exception exception);
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IR::ResultAndCarry<IR::U32> EmitImmShift(IR::U32 value, ShiftType type, Imm<5> imm5, IR::U1 carry_in);
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// thumb16
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bool thumb16_LSL_imm(Imm<5> imm5, Reg m, Reg d);
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bool thumb16_LSR_imm(Imm<5> imm5, Reg m, Reg d);
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@ -167,8 +169,18 @@ struct ThumbTranslatorVisitor final {
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bool thumb32_RSB_imm(Imm<1> i, bool S, Reg n, Imm<3> imm3, Reg d, Imm<8> imm8);
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// thumb32 data processing (plain binary immediate) instructions.
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bool thumb32_ADD_imm_2(Imm<1> imm1, Imm<3> imm3, Reg d, Imm<8> imm8);
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bool thumb32_BFC(Imm<3> imm3, Reg d, Imm<2> imm2, Imm<5> msb);
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bool thumb32_BFI(Reg n, Imm<3> imm3, Reg d, Imm<2> imm2, Imm<5> msb);
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bool thumb32_MOVT(Imm<1> imm1, Imm<4> imm4, Imm<3> imm3, Reg d, Imm<8> imm8);
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bool thumb32_MOVW_imm(Imm<1> imm1, Imm<4> imm4, Imm<3> imm3, Reg d, Imm<8> imm8);
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bool thumb32_SBFX(Reg n, Imm<3> imm3, Reg d, Imm<2> imm2, Imm<5> widthm1);
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bool thumb32_SSAT(bool sh, Reg n, Imm<3> imm3, Reg d, Imm<2> imm2, Imm<5> sat_imm);
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bool thumb32_SSAT16(Reg n, Reg d, Imm<4> sat_imm);
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bool thumb32_SUB_imm_2(Imm<1> imm1, Imm<3> imm3, Reg d, Imm<8> imm8);
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bool thumb32_UBFX(Reg n, Imm<3> imm3, Reg d, Imm<2> imm2, Imm<5> widthm1);
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bool thumb32_USAT(bool sh, Reg n, Imm<3> imm3, Reg d, Imm<2> imm2, Imm<5> sat_imm);
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bool thumb32_USAT16(Reg n, Reg d, Imm<4> sat_imm);
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// thumb32 miscellaneous control instructions
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bool thumb32_BXJ(Reg m);
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@ -176,4 +176,25 @@ bool ThumbTranslatorVisitor::RaiseException(Exception exception) {
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return false;
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}
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IR::ResultAndCarry<IR::U32> ThumbTranslatorVisitor::EmitImmShift(IR::U32 value, ShiftType type, Imm<5> imm5, IR::U1 carry_in) {
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u8 imm5_value = imm5.ZeroExtend<u8>();
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switch (type) {
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case ShiftType::LSL:
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return ir.LogicalShiftLeft(value, ir.Imm8(imm5_value), carry_in);
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case ShiftType::LSR:
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imm5_value = imm5_value ? imm5_value : 32;
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return ir.LogicalShiftRight(value, ir.Imm8(imm5_value), carry_in);
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case ShiftType::ASR:
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imm5_value = imm5_value ? imm5_value : 32;
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return ir.ArithmeticShiftRight(value, ir.Imm8(imm5_value), carry_in);
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case ShiftType::ROR:
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if (imm5_value) {
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return ir.RotateRight(value, ir.Imm8(imm5_value), carry_in);
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} else {
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return ir.RotateRightExtended(value, carry_in);
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}
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}
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UNREACHABLE();
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}
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} // namespace Dynarmic::A32
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