Fix VShift terminology
An arithmetic shift is by definition a signed shift, and a logical shift is by definition an unsigned shift. - Rename VectorLogicalVShiftS* -> VectorArithmeticVShift* - Rename VectorLogicalVShiftU* -> VectorLogicalVShift*
This commit is contained in:
MerryMage
parent
b51dae790d
commit
f0920c0ded
6 changed files with 170 additions and 170 deletions
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@ -510,6 +510,134 @@ void EmitX64::EmitVectorArithmeticShiftRight64(EmitContext& ctx, IR::Inst* inst)
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ctx.reg_alloc.DefineValue(inst, result);
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}
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template <typename T>
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static constexpr T VShift(T x, T y) {
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const s8 shift_amount = static_cast<s8>(static_cast<u8>(y));
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const s64 bit_size = static_cast<s64>(Common::BitSize<T>());
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if constexpr (std::is_signed_v<T>) {
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if (shift_amount >= bit_size) {
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return 0;
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}
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if (shift_amount <= -bit_size) {
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// Parentheses necessary, as MSVC doesn't appear to consider cast parentheses
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// as a grouping in terms of precedence, causing warning C4554 to fire. See:
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// https://developercommunity.visualstudio.com/content/problem/144783/msvc-2017-does-not-understand-that-static-cast-cou.html
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return x >> (T(bit_size - 1));
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}
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} else if (shift_amount <= -bit_size || shift_amount >= bit_size) {
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return 0;
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}
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if (shift_amount < 0) {
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return x >> T(-shift_amount);
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}
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using unsigned_type = std::make_unsigned_t<T>;
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return static_cast<T>(static_cast<unsigned_type>(x) << static_cast<unsigned_type>(shift_amount));
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}
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void EmitX64::EmitVectorArithmeticVShift8(EmitContext& ctx, IR::Inst* inst) {
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EmitTwoArgumentFallback(code, ctx, inst, [](VectorArray<s8>& result, const VectorArray<s8>& a, const VectorArray<s8>& b) {
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std::transform(a.begin(), a.end(), b.begin(), result.begin(), VShift<s8>);
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});
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}
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void EmitX64::EmitVectorArithmeticVShift16(EmitContext& ctx, IR::Inst* inst) {
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if (code.DoesCpuSupport(Xbyak::util::Cpu::tAVX512VL) && code.DoesCpuSupport(Xbyak::util::Cpu::tAVX512BW)) {
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auto args = ctx.reg_alloc.GetArgumentInfo(inst);
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const Xbyak::Xmm result = ctx.reg_alloc.UseScratchXmm(args[0]);
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const Xbyak::Xmm left_shift = ctx.reg_alloc.UseScratchXmm(args[1]);
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const Xbyak::Xmm right_shift = ctx.reg_alloc.ScratchXmm();
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const Xbyak::Xmm tmp = ctx.reg_alloc.ScratchXmm();
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code.vmovdqa(tmp, code.MConst(xword, 0x00FF00FF00FF00FF, 0x00FF00FF00FF00FF));
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code.vpxor(right_shift, right_shift, right_shift);
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code.vpsubw(right_shift, right_shift, left_shift);
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code.vpsllw(xmm0, left_shift, 8);
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code.vpsraw(xmm0, xmm0, 15);
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code.vpand(right_shift, right_shift, tmp);
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code.vpand(left_shift, left_shift, tmp);
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code.vpsravw(tmp, result, right_shift);
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code.vpsllvw(result, result, left_shift);
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code.pblendvb(result, tmp);
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ctx.reg_alloc.DefineValue(inst, result);
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return;
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}
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EmitTwoArgumentFallback(code, ctx, inst, [](VectorArray<s16>& result, const VectorArray<s16>& a, const VectorArray<s16>& b) {
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std::transform(a.begin(), a.end(), b.begin(), result.begin(), VShift<s16>);
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});
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}
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void EmitX64::EmitVectorArithmeticVShift32(EmitContext& ctx, IR::Inst* inst) {
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if (code.DoesCpuSupport(Xbyak::util::Cpu::tAVX2)) {
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auto args = ctx.reg_alloc.GetArgumentInfo(inst);
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const Xbyak::Xmm result = ctx.reg_alloc.UseScratchXmm(args[0]);
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const Xbyak::Xmm left_shift = ctx.reg_alloc.UseScratchXmm(args[1]);
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const Xbyak::Xmm right_shift = ctx.reg_alloc.ScratchXmm();
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const Xbyak::Xmm tmp = ctx.reg_alloc.ScratchXmm();
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code.vmovdqa(tmp, code.MConst(xword, 0x000000FF000000FF, 0x000000FF000000FF));
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code.vpxor(right_shift, right_shift, right_shift);
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code.vpsubd(right_shift, right_shift, left_shift);
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code.vpslld(xmm0, left_shift, 24);
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code.vpand(right_shift, right_shift, tmp);
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code.vpand(left_shift, left_shift, tmp);
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code.vpsravd(tmp, result, right_shift);
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code.vpsllvd(result, result, left_shift);
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code.blendvps(result, tmp);
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ctx.reg_alloc.DefineValue(inst, result);
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return;
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}
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EmitTwoArgumentFallback(code, ctx, inst, [](VectorArray<s32>& result, const VectorArray<s32>& a, const VectorArray<s32>& b) {
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std::transform(a.begin(), a.end(), b.begin(), result.begin(), VShift<s32>);
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});
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}
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void EmitX64::EmitVectorArithmeticVShift64(EmitContext& ctx, IR::Inst* inst) {
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if (code.DoesCpuSupport(Xbyak::util::Cpu::tAVX512F) && code.DoesCpuSupport(Xbyak::util::Cpu::tAVX512VL)) {
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auto args = ctx.reg_alloc.GetArgumentInfo(inst);
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const Xbyak::Xmm result = ctx.reg_alloc.UseScratchXmm(args[0]);
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const Xbyak::Xmm left_shift = ctx.reg_alloc.UseScratchXmm(args[1]);
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const Xbyak::Xmm right_shift = ctx.reg_alloc.ScratchXmm();
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const Xbyak::Xmm tmp = ctx.reg_alloc.ScratchXmm();
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code.vmovdqa(tmp, code.MConst(xword, 0x00000000000000FF, 0x00000000000000FF));
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code.vpxor(right_shift, right_shift, right_shift);
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code.vpsubq(right_shift, right_shift, left_shift);
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code.vpsllq(xmm0, left_shift, 56);
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code.vpand(right_shift, right_shift, tmp);
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code.vpand(left_shift, left_shift, tmp);
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code.vpsravq(tmp, result, right_shift);
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code.vpsllvq(result, result, left_shift);
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code.blendvpd(result, tmp);
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ctx.reg_alloc.DefineValue(inst, result);
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return;
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}
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EmitTwoArgumentFallback(code, ctx, inst, [](VectorArray<s64>& result, const VectorArray<s64>& a, const VectorArray<s64>& b) {
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std::transform(a.begin(), a.end(), b.begin(), result.begin(), VShift<s64>);
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});
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}
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void EmitX64::EmitVectorBroadcastLower8(EmitContext& ctx, IR::Inst* inst) {
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auto args = ctx.reg_alloc.GetArgumentInfo(inst);
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@ -1336,141 +1464,13 @@ void EmitX64::EmitVectorLogicalShiftRight64(EmitContext& ctx, IR::Inst* inst) {
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ctx.reg_alloc.DefineValue(inst, result);
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}
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template <typename T>
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static constexpr T LogicalVShift(T x, T y) {
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const s8 shift_amount = static_cast<s8>(static_cast<u8>(y));
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const s64 bit_size = static_cast<s64>(Common::BitSize<T>());
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if constexpr (std::is_signed_v<T>) {
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if (shift_amount >= bit_size) {
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return 0;
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}
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if (shift_amount <= -bit_size) {
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// Parentheses necessary, as MSVC doesn't appear to consider cast parentheses
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// as a grouping in terms of precedence, causing warning C4554 to fire. See:
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// https://developercommunity.visualstudio.com/content/problem/144783/msvc-2017-does-not-understand-that-static-cast-cou.html
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return x >> (T(bit_size - 1));
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}
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} else if (shift_amount <= -bit_size || shift_amount >= bit_size) {
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return 0;
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}
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if (shift_amount < 0) {
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return x >> T(-shift_amount);
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}
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using unsigned_type = std::make_unsigned_t<T>;
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return static_cast<T>(static_cast<unsigned_type>(x) << static_cast<unsigned_type>(shift_amount));
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}
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void EmitX64::EmitVectorLogicalVShiftS8(EmitContext& ctx, IR::Inst* inst) {
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EmitTwoArgumentFallback(code, ctx, inst, [](VectorArray<s8>& result, const VectorArray<s8>& a, const VectorArray<s8>& b) {
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std::transform(a.begin(), a.end(), b.begin(), result.begin(), LogicalVShift<s8>);
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});
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}
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void EmitX64::EmitVectorLogicalVShiftS16(EmitContext& ctx, IR::Inst* inst) {
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if (code.DoesCpuSupport(Xbyak::util::Cpu::tAVX512VL) && code.DoesCpuSupport(Xbyak::util::Cpu::tAVX512BW)) {
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auto args = ctx.reg_alloc.GetArgumentInfo(inst);
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const Xbyak::Xmm result = ctx.reg_alloc.UseScratchXmm(args[0]);
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const Xbyak::Xmm left_shift = ctx.reg_alloc.UseScratchXmm(args[1]);
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const Xbyak::Xmm right_shift = ctx.reg_alloc.ScratchXmm();
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const Xbyak::Xmm tmp = ctx.reg_alloc.ScratchXmm();
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code.vmovdqa(tmp, code.MConst(xword, 0x00FF00FF00FF00FF, 0x00FF00FF00FF00FF));
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code.vpxor(right_shift, right_shift, right_shift);
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code.vpsubw(right_shift, right_shift, left_shift);
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code.vpsllw(xmm0, left_shift, 8);
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code.vpsraw(xmm0, xmm0, 15);
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code.vpand(right_shift, right_shift, tmp);
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code.vpand(left_shift, left_shift, tmp);
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code.vpsravw(tmp, result, right_shift);
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code.vpsllvw(result, result, left_shift);
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code.pblendvb(result, tmp);
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ctx.reg_alloc.DefineValue(inst, result);
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return;
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}
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EmitTwoArgumentFallback(code, ctx, inst, [](VectorArray<s16>& result, const VectorArray<s16>& a, const VectorArray<s16>& b) {
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std::transform(a.begin(), a.end(), b.begin(), result.begin(), LogicalVShift<s16>);
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});
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}
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void EmitX64::EmitVectorLogicalVShiftS32(EmitContext& ctx, IR::Inst* inst) {
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if (code.DoesCpuSupport(Xbyak::util::Cpu::tAVX2)) {
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auto args = ctx.reg_alloc.GetArgumentInfo(inst);
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const Xbyak::Xmm result = ctx.reg_alloc.UseScratchXmm(args[0]);
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const Xbyak::Xmm left_shift = ctx.reg_alloc.UseScratchXmm(args[1]);
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const Xbyak::Xmm right_shift = ctx.reg_alloc.ScratchXmm();
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const Xbyak::Xmm tmp = ctx.reg_alloc.ScratchXmm();
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code.vmovdqa(tmp, code.MConst(xword, 0x000000FF000000FF, 0x000000FF000000FF));
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code.vpxor(right_shift, right_shift, right_shift);
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code.vpsubd(right_shift, right_shift, left_shift);
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code.vpslld(xmm0, left_shift, 24);
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code.vpand(right_shift, right_shift, tmp);
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code.vpand(left_shift, left_shift, tmp);
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code.vpsravd(tmp, result, right_shift);
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code.vpsllvd(result, result, left_shift);
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code.blendvps(result, tmp);
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ctx.reg_alloc.DefineValue(inst, result);
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return;
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}
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EmitTwoArgumentFallback(code, ctx, inst, [](VectorArray<s32>& result, const VectorArray<s32>& a, const VectorArray<s32>& b) {
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std::transform(a.begin(), a.end(), b.begin(), result.begin(), LogicalVShift<s32>);
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});
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}
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void EmitX64::EmitVectorLogicalVShiftS64(EmitContext& ctx, IR::Inst* inst) {
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if (code.DoesCpuSupport(Xbyak::util::Cpu::tAVX512F) && code.DoesCpuSupport(Xbyak::util::Cpu::tAVX512VL)) {
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auto args = ctx.reg_alloc.GetArgumentInfo(inst);
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const Xbyak::Xmm result = ctx.reg_alloc.UseScratchXmm(args[0]);
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const Xbyak::Xmm left_shift = ctx.reg_alloc.UseScratchXmm(args[1]);
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const Xbyak::Xmm right_shift = ctx.reg_alloc.ScratchXmm();
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const Xbyak::Xmm tmp = ctx.reg_alloc.ScratchXmm();
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code.vmovdqa(tmp, code.MConst(xword, 0x00000000000000FF, 0x00000000000000FF));
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code.vpxor(right_shift, right_shift, right_shift);
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code.vpsubq(right_shift, right_shift, left_shift);
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code.vpsllq(xmm0, left_shift, 56);
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code.vpand(right_shift, right_shift, tmp);
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code.vpand(left_shift, left_shift, tmp);
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code.vpsravq(tmp, result, right_shift);
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code.vpsllvq(result, result, left_shift);
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code.blendvpd(result, tmp);
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ctx.reg_alloc.DefineValue(inst, result);
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return;
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}
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EmitTwoArgumentFallback(code, ctx, inst, [](VectorArray<s64>& result, const VectorArray<s64>& a, const VectorArray<s64>& b) {
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std::transform(a.begin(), a.end(), b.begin(), result.begin(), LogicalVShift<s64>);
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});
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}
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void EmitX64::EmitVectorLogicalVShiftU8(EmitContext& ctx, IR::Inst* inst) {
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void EmitX64::EmitVectorLogicalVShift8(EmitContext& ctx, IR::Inst* inst) {
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EmitTwoArgumentFallback(code, ctx, inst, [](VectorArray<u8>& result, const VectorArray<u8>& a, const VectorArray<u8>& b) {
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std::transform(a.begin(), a.end(), b.begin(), result.begin(), LogicalVShift<u8>);
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std::transform(a.begin(), a.end(), b.begin(), result.begin(), VShift<u8>);
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});
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}
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void EmitX64::EmitVectorLogicalVShiftU16(EmitContext& ctx, IR::Inst* inst) {
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void EmitX64::EmitVectorLogicalVShift16(EmitContext& ctx, IR::Inst* inst) {
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if (code.DoesCpuSupport(Xbyak::util::Cpu::tAVX512VL) && code.DoesCpuSupport(Xbyak::util::Cpu::tAVX512BW)) {
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auto args = ctx.reg_alloc.GetArgumentInfo(inst);
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@ -1494,11 +1494,11 @@ void EmitX64::EmitVectorLogicalVShiftU16(EmitContext& ctx, IR::Inst* inst) {
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}
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EmitTwoArgumentFallback(code, ctx, inst, [](VectorArray<u16>& result, const VectorArray<u16>& a, const VectorArray<u16>& b) {
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std::transform(a.begin(), a.end(), b.begin(), result.begin(), LogicalVShift<u16>);
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std::transform(a.begin(), a.end(), b.begin(), result.begin(), VShift<u16>);
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});
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}
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void EmitX64::EmitVectorLogicalVShiftU32(EmitContext& ctx, IR::Inst* inst) {
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void EmitX64::EmitVectorLogicalVShift32(EmitContext& ctx, IR::Inst* inst) {
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if (code.DoesCpuSupport(Xbyak::util::Cpu::tAVX2)) {
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auto args = ctx.reg_alloc.GetArgumentInfo(inst);
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@ -1522,11 +1522,11 @@ void EmitX64::EmitVectorLogicalVShiftU32(EmitContext& ctx, IR::Inst* inst) {
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}
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EmitTwoArgumentFallback(code, ctx, inst, [](VectorArray<u32>& result, const VectorArray<u32>& a, const VectorArray<u32>& b) {
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std::transform(a.begin(), a.end(), b.begin(), result.begin(), LogicalVShift<u32>);
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std::transform(a.begin(), a.end(), b.begin(), result.begin(), VShift<u32>);
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});
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}
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void EmitX64::EmitVectorLogicalVShiftU64(EmitContext& ctx, IR::Inst* inst) {
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void EmitX64::EmitVectorLogicalVShift64(EmitContext& ctx, IR::Inst* inst) {
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if (code.DoesCpuSupport(Xbyak::util::Cpu::tAVX2)) {
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auto args = ctx.reg_alloc.GetArgumentInfo(inst);
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@ -1550,7 +1550,7 @@ void EmitX64::EmitVectorLogicalVShiftU64(EmitContext& ctx, IR::Inst* inst) {
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}
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EmitTwoArgumentFallback(code, ctx, inst, [](VectorArray<u64>& result, const VectorArray<u64>& a, const VectorArray<u64>& b) {
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std::transform(a.begin(), a.end(), b.begin(), result.begin(), LogicalVShift<u64>);
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std::transform(a.begin(), a.end(), b.begin(), result.begin(), VShift<u64>);
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});
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}
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@ -330,7 +330,7 @@ bool TranslatorVisitor::SSHL_1(Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
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const IR::U128 operand1 = V(64, Vn);
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const IR::U128 operand2 = V(64, Vm);
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const IR::U128 result = ir.VectorLogicalVShiftSigned(64, operand1, operand2);
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const IR::U128 result = ir.VectorArithmeticVShift(64, operand1, operand2);
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V(64, Vd, result);
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return true;
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@ -361,7 +361,7 @@ bool TranslatorVisitor::USHL_1(Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
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const IR::U128 operand1 = V(64, Vn);
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const IR::U128 operand2 = V(64, Vm);
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const IR::U128 result = ir.VectorLogicalVShiftUnsigned(64, operand1, operand2);
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const IR::U128 result = ir.VectorLogicalVShift(64, operand1, operand2);
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V(64, Vd, result);
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return true;
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@ -817,7 +817,7 @@ bool TranslatorVisitor::SSHL_2(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
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const IR::U128 operand1 = V(datasize, Vn);
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const IR::U128 operand2 = V(datasize, Vm);
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const IR::U128 result = ir.VectorLogicalVShiftSigned(esize, operand1, operand2);
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const IR::U128 result = ir.VectorArithmeticVShift(esize, operand1, operand2);
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V(datasize, Vd, result);
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return true;
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}
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@ -839,7 +839,7 @@ bool TranslatorVisitor::USHL_2(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
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const IR::U128 operand1 = V(datasize, Vn);
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const IR::U128 operand2 = V(datasize, Vm);
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const IR::U128 result = ir.VectorLogicalVShiftUnsigned(esize, operand1, operand2);
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const IR::U128 result = ir.VectorLogicalVShift(esize, operand1, operand2);
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V(datasize, Vd, result);
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return true;
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}
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@ -888,6 +888,21 @@ U128 IREmitter::VectorArithmeticShiftRight(size_t esize, const U128& a, u8 shift
|
|||
return {};
|
||||
}
|
||||
|
||||
U128 IREmitter::VectorArithmeticVShift(size_t esize, const U128& a, const U128& b) {
|
||||
switch (esize) {
|
||||
case 8:
|
||||
return Inst<U128>(Opcode::VectorArithmeticVShift8, a, b);
|
||||
case 16:
|
||||
return Inst<U128>(Opcode::VectorArithmeticVShift16, a, b);
|
||||
case 32:
|
||||
return Inst<U128>(Opcode::VectorArithmeticVShift32, a, b);
|
||||
case 64:
|
||||
return Inst<U128>(Opcode::VectorArithmeticVShift64, a, b);
|
||||
}
|
||||
UNREACHABLE();
|
||||
return {};
|
||||
}
|
||||
|
||||
U128 IREmitter::VectorBroadcastLower(size_t esize, const UAny& a) {
|
||||
switch (esize) {
|
||||
case 8:
|
||||
|
|
@ -1145,31 +1160,16 @@ U128 IREmitter::VectorLogicalShiftRight(size_t esize, const U128& a, u8 shift_am
|
|||
return {};
|
||||
}
|
||||
|
||||
U128 IREmitter::VectorLogicalVShiftSigned(size_t esize, const U128& a, const U128& b) {
|
||||
U128 IREmitter::VectorLogicalVShift(size_t esize, const U128& a, const U128& b) {
|
||||
switch (esize) {
|
||||
case 8:
|
||||
return Inst<U128>(Opcode::VectorLogicalVShiftS8, a, b);
|
||||
return Inst<U128>(Opcode::VectorLogicalVShift8, a, b);
|
||||
case 16:
|
||||
return Inst<U128>(Opcode::VectorLogicalVShiftS16, a, b);
|
||||
return Inst<U128>(Opcode::VectorLogicalVShift16, a, b);
|
||||
case 32:
|
||||
return Inst<U128>(Opcode::VectorLogicalVShiftS32, a, b);
|
||||
return Inst<U128>(Opcode::VectorLogicalVShift32, a, b);
|
||||
case 64:
|
||||
return Inst<U128>(Opcode::VectorLogicalVShiftS64, a, b);
|
||||
}
|
||||
UNREACHABLE();
|
||||
return {};
|
||||
}
|
||||
|
||||
U128 IREmitter::VectorLogicalVShiftUnsigned(size_t esize, const U128& a, const U128& b) {
|
||||
switch (esize) {
|
||||
case 8:
|
||||
return Inst<U128>(Opcode::VectorLogicalVShiftU8, a, b);
|
||||
case 16:
|
||||
return Inst<U128>(Opcode::VectorLogicalVShiftU16, a, b);
|
||||
case 32:
|
||||
return Inst<U128>(Opcode::VectorLogicalVShiftU32, a, b);
|
||||
case 64:
|
||||
return Inst<U128>(Opcode::VectorLogicalVShiftU64, a, b);
|
||||
return Inst<U128>(Opcode::VectorLogicalVShift64, a, b);
|
||||
}
|
||||
UNREACHABLE();
|
||||
return {};
|
||||
|
|
|
|||
|
|
@ -212,6 +212,7 @@ public:
|
|||
U128 VectorAdd(size_t esize, const U128& a, const U128& b);
|
||||
U128 VectorAnd(const U128& a, const U128& b);
|
||||
U128 VectorArithmeticShiftRight(size_t esize, const U128& a, u8 shift_amount);
|
||||
U128 VectorArithmeticVShift(size_t esize, const U128& a, const U128& b);
|
||||
U128 VectorBroadcast(size_t esize, const UAny& a);
|
||||
U128 VectorBroadcastLower(size_t esize, const UAny& a);
|
||||
U128 VectorCountLeadingZeros(size_t esize, const U128& a);
|
||||
|
|
@ -237,8 +238,7 @@ public:
|
|||
U128 VectorLessUnsigned(size_t esize, const U128& a, const U128& b);
|
||||
U128 VectorLogicalShiftLeft(size_t esize, const U128& a, u8 shift_amount);
|
||||
U128 VectorLogicalShiftRight(size_t esize, const U128& a, u8 shift_amount);
|
||||
U128 VectorLogicalVShiftSigned(size_t esize, const U128& a, const U128& b);
|
||||
U128 VectorLogicalVShiftUnsigned(size_t esize, const U128& a, const U128& b);
|
||||
U128 VectorLogicalVShift(size_t esize, const U128& a, const U128& b);
|
||||
U128 VectorMaxSigned(size_t esize, const U128& a, const U128& b);
|
||||
U128 VectorMaxUnsigned(size_t esize, const U128& a, const U128& b);
|
||||
U128 VectorMinSigned(size_t esize, const U128& a, const U128& b);
|
||||
|
|
|
|||
|
|
@ -253,6 +253,10 @@ OPCODE(VectorArithmeticShiftRight8, U128, U128
|
|||
OPCODE(VectorArithmeticShiftRight16, U128, U128, U8 )
|
||||
OPCODE(VectorArithmeticShiftRight32, U128, U128, U8 )
|
||||
OPCODE(VectorArithmeticShiftRight64, U128, U128, U8 )
|
||||
OPCODE(VectorArithmeticVShift8, U128, U128, U128 )
|
||||
OPCODE(VectorArithmeticVShift16, U128, U128, U128 )
|
||||
OPCODE(VectorArithmeticVShift32, U128, U128, U128 )
|
||||
OPCODE(VectorArithmeticVShift64, U128, U128, U128 )
|
||||
OPCODE(VectorBroadcastLower8, U128, U8 )
|
||||
OPCODE(VectorBroadcastLower16, U128, U16 )
|
||||
OPCODE(VectorBroadcastLower32, U128, U32 )
|
||||
|
|
@ -311,14 +315,10 @@ OPCODE(VectorLogicalShiftRight8, U128, U128
|
|||
OPCODE(VectorLogicalShiftRight16, U128, U128, U8 )
|
||||
OPCODE(VectorLogicalShiftRight32, U128, U128, U8 )
|
||||
OPCODE(VectorLogicalShiftRight64, U128, U128, U8 )
|
||||
OPCODE(VectorLogicalVShiftS8, U128, U128, U128 )
|
||||
OPCODE(VectorLogicalVShiftS16, U128, U128, U128 )
|
||||
OPCODE(VectorLogicalVShiftS32, U128, U128, U128 )
|
||||
OPCODE(VectorLogicalVShiftS64, U128, U128, U128 )
|
||||
OPCODE(VectorLogicalVShiftU8, U128, U128, U128 )
|
||||
OPCODE(VectorLogicalVShiftU16, U128, U128, U128 )
|
||||
OPCODE(VectorLogicalVShiftU32, U128, U128, U128 )
|
||||
OPCODE(VectorLogicalVShiftU64, U128, U128, U128 )
|
||||
OPCODE(VectorLogicalVShift8, U128, U128, U128 )
|
||||
OPCODE(VectorLogicalVShift16, U128, U128, U128 )
|
||||
OPCODE(VectorLogicalVShift32, U128, U128, U128 )
|
||||
OPCODE(VectorLogicalVShift64, U128, U128, U128 )
|
||||
OPCODE(VectorMaxS8, U128, U128, U128 )
|
||||
OPCODE(VectorMaxS16, U128, U128, U128 )
|
||||
OPCODE(VectorMaxS32, U128, U128, U128 )
|
||||
|
|
|
|||
Loading…
Reference in a new issue