backend/x64: Reduce races on invalidation requests in interface
This situation occurs when RequestCacheInvalidation is called from multiple threads. This results in unusual issues around memory allocation which arise from concurrent access to invalid_cache_ranges. There are several reasons for this: 1. No locking around the invalidation queue. 2. is_executing is not multithread safe. So here we reduce any cache clear or any invalidation to raise a CacheInvalidation halt, which we execute immediately before or immediately after Run() instead.
This commit is contained in:
Merry
parent
6d0995c948
commit
ee84ec0bb9
2 changed files with 179 additions and 134 deletions
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@ -5,6 +5,7 @@
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#include <functional>
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#include <memory>
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#include <mutex>
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#include <boost/icl/interval_set.hpp>
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#include <fmt/format.h>
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@ -66,18 +67,17 @@ struct Jit::Impl {
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, conf(std::move(conf))
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, jit_interface(jit) {}
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A32JitState jit_state;
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BlockOfCode block_of_code;
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A32EmitX64 emitter;
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Optimization::PolyfillOptions polyfill_options;
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~Impl() = default;
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const A32::UserConfig conf;
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HaltReason Run() {
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ASSERT(!jit_interface->is_executing);
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PerformRequestedCacheInvalidation(static_cast<HaltReason>(Atomic::Load(&jit_state.halt_reason)));
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// Requests made during execution to invalidate the cache are queued up here.
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boost::icl::interval_set<u32> invalid_cache_ranges;
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bool invalidate_entire_cache = false;
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jit_interface->is_executing = true;
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SCOPE_EXIT {
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jit_interface->is_executing = false;
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};
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HaltReason Execute() {
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const CodePtr current_codeptr = [this] {
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// RSB optimization
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const u32 new_rsb_ptr = (jit_state.rsb_ptr - 1) & A32JitState::RSBPtrMask;
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@ -89,11 +89,44 @@ struct Jit::Impl {
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return GetCurrentBlock();
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}();
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return block_of_code.RunCode(&jit_state, current_codeptr);
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const HaltReason hr = block_of_code.RunCode(&jit_state, current_codeptr);
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PerformRequestedCacheInvalidation(hr);
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return hr;
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}
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HaltReason Step() {
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return block_of_code.StepCode(&jit_state, GetCurrentSingleStep());
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ASSERT(!jit_interface->is_executing);
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PerformRequestedCacheInvalidation(static_cast<HaltReason>(Atomic::Load(&jit_state.halt_reason)));
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jit_interface->is_executing = true;
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SCOPE_EXIT {
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jit_interface->is_executing = false;
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};
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const HaltReason hr = block_of_code.StepCode(&jit_state, GetCurrentSingleStep());
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PerformRequestedCacheInvalidation(hr);
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return hr;
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}
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void ClearCache() {
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std::unique_lock lock{invalidation_mutex};
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invalidate_entire_cache = true;
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HaltExecution(HaltReason::CacheInvalidation);
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}
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void InvalidateCacheRange(std::uint32_t start_address, std::size_t length) {
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std::unique_lock lock{invalidation_mutex};
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invalid_cache_ranges.add(boost::icl::discrete_interval<u32>::closed(start_address, static_cast<u32>(start_address + length - 1)));
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HaltExecution(HaltReason::CacheInvalidation);
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}
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void Reset() {
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ASSERT(!jit_interface->is_executing);
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jit_state = {};
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}
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void HaltExecution(HaltReason hr) {
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@ -108,38 +141,49 @@ struct Jit::Impl {
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jit_state.exclusive_state = 0;
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}
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void PerformCacheInvalidation() {
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if (invalidate_entire_cache) {
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jit_state.ResetRSB();
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block_of_code.ClearCache();
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emitter.ClearCache();
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invalid_cache_ranges.clear();
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invalidate_entire_cache = false;
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return;
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}
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if (invalid_cache_ranges.empty()) {
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return;
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}
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jit_state.ResetRSB();
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emitter.InvalidateCacheRanges(invalid_cache_ranges);
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invalid_cache_ranges.clear();
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std::array<u32, 16>& Regs() {
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return jit_state.Reg;
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}
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void RequestCacheInvalidation() {
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if (jit_interface->is_executing) {
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HaltExecution(HaltReason::CacheInvalidation);
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return;
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}
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const std::array<u32, 16>& Regs() const {
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return jit_state.Reg;
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}
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PerformCacheInvalidation();
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std::array<u32, 64>& ExtRegs() {
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return jit_state.ExtReg;
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}
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const std::array<u32, 64>& ExtRegs() const {
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return jit_state.ExtReg;
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}
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u32 Cpsr() const {
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return jit_state.Cpsr();
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}
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void SetCpsr(u32 value) {
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return jit_state.SetCpsr(value);
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}
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u32 Fpscr() const {
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return jit_state.Fpscr();
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}
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void SetFpscr(u32 value) {
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return jit_state.SetFpscr(value);
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}
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void DumpDisassembly() const {
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const size_t size = reinterpret_cast<const char*>(block_of_code.getCurr()) - reinterpret_cast<const char*>(block_of_code.GetCodeBegin());
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Common::DumpDisassembledX64(block_of_code.GetCodeBegin(), size);
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}
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std::vector<std::string> Disassemble() const {
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const size_t size = reinterpret_cast<const char*>(block_of_code.getCurr()) - reinterpret_cast<const char*>(block_of_code.GetCodeBegin());
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return Common::DisassembleX64(block_of_code.GetCodeBegin(), size);
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}
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private:
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Jit* jit_interface;
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static CodePtr GetCurrentBlockThunk(void* this_voidptr) {
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Jit::Impl& this_ = *static_cast<Jit::Impl*>(this_voidptr);
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return this_.GetCurrentBlock();
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@ -165,7 +209,7 @@ private:
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constexpr size_t MINIMUM_REMAINING_CODESIZE = 1 * 1024 * 1024;
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if (block_of_code.SpaceRemaining() < MINIMUM_REMAINING_CODESIZE) {
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invalidate_entire_cache = true;
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PerformCacheInvalidation();
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PerformRequestedCacheInvalidation(HaltReason::CacheInvalidation);
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}
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block_of_code.EnsureMemoryCommitted(MINIMUM_REMAINING_CODESIZE);
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@ -185,6 +229,42 @@ private:
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Optimization::VerificationPass(ir_block);
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return emitter.Emit(ir_block);
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}
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void PerformRequestedCacheInvalidation(HaltReason hr) {
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if (Has(hr, HaltReason::CacheInvalidation)) {
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std::unique_lock lock{invalidation_mutex};
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ClearHalt(HaltReason::CacheInvalidation);
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if (!invalidate_entire_cache && invalid_cache_ranges.empty()) {
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return;
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}
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jit_state.ResetRSB();
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if (invalidate_entire_cache) {
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block_of_code.ClearCache();
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emitter.ClearCache();
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} else {
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emitter.InvalidateCacheRanges(invalid_cache_ranges);
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}
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invalid_cache_ranges.clear();
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invalidate_entire_cache = false;
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}
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}
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A32JitState jit_state;
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BlockOfCode block_of_code;
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A32EmitX64 emitter;
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Optimization::PolyfillOptions polyfill_options;
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const A32::UserConfig conf;
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Jit* jit_interface;
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// Requests made during execution to invalidate the cache are queued up here.
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bool invalidate_entire_cache = false;
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boost::icl::interval_set<u32> invalid_cache_ranges;
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std::mutex invalidation_mutex;
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};
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Jit::Jit(UserConfig conf)
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@ -193,46 +273,23 @@ Jit::Jit(UserConfig conf)
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Jit::~Jit() = default;
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HaltReason Jit::Run() {
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ASSERT(!is_executing);
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is_executing = true;
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SCOPE_EXIT {
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this->is_executing = false;
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};
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const HaltReason hr = impl->Execute();
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impl->PerformCacheInvalidation();
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return hr;
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return impl->Run();
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}
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HaltReason Jit::Step() {
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ASSERT(!is_executing);
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is_executing = true;
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SCOPE_EXIT {
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this->is_executing = false;
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};
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const HaltReason hr = impl->Step();
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impl->PerformCacheInvalidation();
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return hr;
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return impl->Step();
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}
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void Jit::ClearCache() {
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impl->invalidate_entire_cache = true;
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impl->RequestCacheInvalidation();
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impl->ClearCache();
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}
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void Jit::InvalidateCacheRange(std::uint32_t start_address, std::size_t length) {
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impl->invalid_cache_ranges.add(boost::icl::discrete_interval<u32>::closed(start_address, static_cast<u32>(start_address + length - 1)));
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impl->RequestCacheInvalidation();
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impl->InvalidateCacheRange(start_address, length);
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}
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void Jit::Reset() {
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ASSERT(!is_executing);
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impl->jit_state = {};
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impl->Reset();
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}
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void Jit::HaltExecution(HaltReason hr) {
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@ -243,48 +300,44 @@ void Jit::ClearHalt(HaltReason hr) {
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impl->ClearHalt(hr);
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}
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std::array<std::uint32_t, 16>& Jit::Regs() {
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return impl->Regs();
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}
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const std::array<std::uint32_t, 16>& Jit::Regs() const {
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return impl->Regs();
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}
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std::array<std::uint32_t, 64>& Jit::ExtRegs() {
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return impl->ExtRegs();
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}
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const std::array<std::uint32_t, 64>& Jit::ExtRegs() const {
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return impl->ExtRegs();
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}
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std::uint32_t Jit::Cpsr() const {
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return impl->Cpsr();
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}
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void Jit::SetCpsr(std::uint32_t value) {
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impl->SetCpsr(value);
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}
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std::uint32_t Jit::Fpscr() const {
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return impl->Fpscr();
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}
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void Jit::SetFpscr(std::uint32_t value) {
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impl->SetFpscr(value);
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}
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void Jit::ClearExclusiveState() {
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impl->ClearExclusiveState();
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}
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std::array<u32, 16>& Jit::Regs() {
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return impl->jit_state.Reg;
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}
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const std::array<u32, 16>& Jit::Regs() const {
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return impl->jit_state.Reg;
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}
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std::array<u32, 64>& Jit::ExtRegs() {
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return impl->jit_state.ExtReg;
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}
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const std::array<u32, 64>& Jit::ExtRegs() const {
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return impl->jit_state.ExtReg;
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}
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u32 Jit::Cpsr() const {
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return impl->jit_state.Cpsr();
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}
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void Jit::SetCpsr(u32 value) {
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return impl->jit_state.SetCpsr(value);
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}
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u32 Jit::Fpscr() const {
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return impl->jit_state.Fpscr();
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}
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void Jit::SetFpscr(u32 value) {
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return impl->jit_state.SetFpscr(value);
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}
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void Jit::DumpDisassembly() const {
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const size_t size = reinterpret_cast<const char*>(impl->block_of_code.getCurr()) - reinterpret_cast<const char*>(impl->block_of_code.GetCodeBegin());
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Common::DumpDisassembledX64(impl->block_of_code.GetCodeBegin(), size);
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impl->DumpDisassembly();
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}
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std::vector<std::string> Jit::Disassemble() const {
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const size_t size = reinterpret_cast<const char*>(impl->block_of_code.getCurr()) - reinterpret_cast<const char*>(impl->block_of_code.GetCodeBegin());
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return Common::DisassembleX64(impl->block_of_code.GetCodeBegin(), size);
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}
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} // namespace Dynarmic::A32
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@ -69,7 +69,7 @@ public:
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HaltReason Run() {
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ASSERT(!is_executing);
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PerformRequestedCacheInvalidation();
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PerformRequestedCacheInvalidation(static_cast<HaltReason>(Atomic::Load(&jit_state.halt_reason)));
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is_executing = true;
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SCOPE_EXIT {
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@ -91,14 +91,14 @@ public:
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const HaltReason hr = block_of_code.RunCode(&jit_state, current_code_ptr);
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PerformRequestedCacheInvalidation();
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PerformRequestedCacheInvalidation(hr);
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return hr;
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}
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HaltReason Step() {
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ASSERT(!is_executing);
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PerformRequestedCacheInvalidation();
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PerformRequestedCacheInvalidation(static_cast<HaltReason>(Atomic::Load(&jit_state.halt_reason)));
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is_executing = true;
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SCOPE_EXIT {
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@ -107,7 +107,7 @@ public:
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const HaltReason hr = block_of_code.StepCode(&jit_state, GetCurrentSingleStep());
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PerformRequestedCacheInvalidation();
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PerformRequestedCacheInvalidation(hr);
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return hr;
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}
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@ -115,9 +115,7 @@ public:
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void ClearCache() {
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std::unique_lock lock{invalidation_mutex};
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invalidate_entire_cache = true;
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if (is_executing) {
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HaltExecution(HaltReason::CacheInvalidation);
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}
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HaltExecution(HaltReason::CacheInvalidation);
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}
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void InvalidateCacheRange(u64 start_address, size_t length) {
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@ -125,9 +123,7 @@ public:
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const auto end_address = static_cast<u64>(start_address + length - 1);
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const auto range = boost::icl::discrete_interval<u64>::closed(start_address, end_address);
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invalid_cache_ranges.add(range);
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if (is_executing) {
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HaltExecution(HaltReason::CacheInvalidation);
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}
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HaltExecution(HaltReason::CacheInvalidation);
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}
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void Reset() {
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@ -268,7 +264,7 @@ private:
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if (block_of_code.SpaceRemaining() < MINIMUM_REMAINING_CODESIZE) {
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// Immediately evacuate cache
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invalidate_entire_cache = true;
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PerformRequestedCacheInvalidation();
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PerformRequestedCacheInvalidation(HaltReason::CacheInvalidation);
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}
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block_of_code.EnsureMemoryCommitted(MINIMUM_REMAINING_CODESIZE);
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@ -294,30 +290,26 @@ private:
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return emitter.Emit(ir_block).entrypoint;
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}
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void RequestCacheInvalidation() {
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if (is_executing) {
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HaltExecution(HaltReason::CacheInvalidation);
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return;
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}
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void PerformRequestedCacheInvalidation(HaltReason hr) {
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if (Has(hr, HaltReason::CacheInvalidation)) {
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std::unique_lock lock{invalidation_mutex};
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PerformRequestedCacheInvalidation();
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}
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ClearHalt(HaltReason::CacheInvalidation);
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void PerformRequestedCacheInvalidation() {
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std::unique_lock lock{invalidation_mutex};
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if (!invalidate_entire_cache && invalid_cache_ranges.empty()) {
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return;
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}
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if (!invalidate_entire_cache && invalid_cache_ranges.empty()) {
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return;
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}
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jit_state.ResetRSB();
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if (invalidate_entire_cache) {
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block_of_code.ClearCache();
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emitter.ClearCache();
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} else {
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emitter.InvalidateCacheRanges(invalid_cache_ranges);
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jit_state.ResetRSB();
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if (invalidate_entire_cache) {
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block_of_code.ClearCache();
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emitter.ClearCache();
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} else {
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emitter.InvalidateCacheRanges(invalid_cache_ranges);
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}
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invalid_cache_ranges.clear();
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invalidate_entire_cache = false;
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}
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invalid_cache_ranges.clear();
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invalidate_entire_cache = false;
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}
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bool is_executing = false;
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