arm: Implement LDRH reg/imm instructions.
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2 changed files with 28 additions and 4 deletions
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@ -185,8 +185,8 @@ boost::optional<const ArmMatcher<V>&> DecodeArm(u32 instruction) {
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//INST(&V::arm_LDRBT, "LDRBT (A2)", "cccc0110u111nnnnttttvvvvvrr0mmmm"),
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//INST(&V::arm_LDRD_imm, "LDRD (imm)", "cccc000pu1w0nnnnddddvvvv1101vvvv"), // v5E
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//INST(&V::arm_LDRD_reg, "LDRD (reg)", "cccc000pu0w0nnnndddd00001101mmmm"), // v5E
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//INST(&V::arm_LDRH_imm, "LDRH (imm)", "cccc000pu1w1nnnnddddvvvv1011vvvv"),
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//INST(&V::arm_LDRH_reg, "LDRH (reg)", "cccc000pu0w1nnnndddd00001011mmmm"),
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INST(&V::arm_LDRH_imm, "LDRH (imm)", "cccc000pu1w1nnnnddddvvvv1011vvvv"),
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INST(&V::arm_LDRH_reg, "LDRH (reg)", "cccc000pu0w1nnnndddd00001011mmmm"),
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//INST(&V::arm_LDRHT, "LDRHT (A1)", "----0000-111------------1011----"),
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//INST(&V::arm_LDRHT, "LDRHT (A2)", "----0000-011--------00001011----"),
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//INST(&V::arm_LDRSB_imm, "LDRSB (imm)", "cccc000pu1w1nnnnddddvvvv1101vvvv"),
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@ -117,11 +117,35 @@ bool ArmTranslatorVisitor::arm_LDRD_reg(Cond cond, bool P, bool U, bool W, Reg n
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}
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bool ArmTranslatorVisitor::arm_LDRH_imm(Cond cond, bool P, bool U, bool W, Reg n, Reg d, Imm4 imm8a, Imm4 imm8b) {
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return InterpretThisInstruction();
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if (ConditionPassed(cond)) {
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const auto data = ir.ReadMemory16(GetAddressingMode(ir, P, U, W, n, ir.Imm32(imm8a << 4 | imm8b)));
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if (d == Reg::PC) {
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ir.ALUWritePC(ir.Add(data, ir.Imm32(4)));
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ir.SetTerm(IR::Term::ReturnToDispatch{});
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return false;
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}
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ir.SetRegister(d, data);
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}
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return true;
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}
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bool ArmTranslatorVisitor::arm_LDRH_reg(Cond cond, bool P, bool U, bool W, Reg n, Reg d, Reg m) {
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return InterpretThisInstruction();
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if (ConditionPassed(cond)) {
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const auto data = ir.ReadMemory16(GetAddressingMode(ir, P, U, W, n, ir.GetRegister(m)));
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if (d == Reg::PC) {
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ir.ALUWritePC(ir.Add(data, ir.Imm32(4)));
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ir.SetTerm(IR::Term::ReturnToDispatch{});
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return false;
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}
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ir.SetRegister(d, data);
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}
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return true;
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}
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bool ArmTranslatorVisitor::arm_LDRHT() {
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