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A64: Implement SRSRA (vector)

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Lioncash 2018-04-07 23:14:20 -04:00 committed by MerryMage
parent bc6016cad7
commit e3d9bf55e7
2 changed files with 14 additions and 1 deletions
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2
src/frontend/A64/decoder/a64.inc
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@ -792,7 +792,7 @@ INST(UnallocatedEncoding, "Unallocated SIMD modified immediate", "0--01
INST(SSHR_2, "SSHR", "0Q0011110IIIIiii000001nnnnnddddd")
INST(SSRA_2, "SSRA", "0Q0011110IIIIiii000101nnnnnddddd")
INST(SRSHR_2, "SRSHR", "0Q0011110IIIIiii001001nnnnnddddd")
//INST(SRSRA_2, "SRSRA", "0Q0011110IIIIiii001101nnnnnddddd")
INST(SRSRA_2, "SRSRA", "0Q0011110IIIIiii001101nnnnnddddd")
INST(SHL_2, "SHL", "0Q0011110IIIIiii010101nnnnnddddd")
//INST(SQSHL_imm_2, "SQSHL (immediate)", "0Q0011110IIIIiii011101nnnnnddddd")
INST(SHRN, "SHRN, SHRN2", "0Q0011110IIIIiii100001nnnnnddddd")

13
src/frontend/A64/translate/impl/simd_shift_by_immediate.cpp
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@ -80,6 +80,19 @@ bool TranslatorVisitor::SRSHR_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd
return true;
}
bool TranslatorVisitor::SRSRA_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) {
if (immh == 0b0000) {
return DecodeError();
}
if (!Q && immh.Bit<3>()) {
return ReservedValue();
}
SignedRoundingShiftRight(*this, Q, immh, immb, Vn, Vd, ShiftExtraBehavior::Accumulate);
return true;
}
bool TranslatorVisitor::SSRA_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) {
if (immh == 0b0000) {
return DecodeError();