A32: Implement SHA256SU1
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3 changed files with 20 additions and 0 deletions
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@ -52,6 +52,7 @@ INST(asimd_VRECPS, "VRECPS", "111100100D0znnnndddd111
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INST(asimd_VRSQRTS, "VRSQRTS", "111100100D1znnnndddd1111NQM1mmmm") // ASIMD
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INST(v8_SHA256H, "SHA256H", "111100110D00nnnndddd1100NQM0mmmm") // v8
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INST(v8_SHA256H2, "SHA256H2", "111100110D01nnnndddd1100NQM0mmmm") // v8
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INST(v8_SHA256SU1, "SHA256SU1", "111100110D10nnnndddd1100NQM0mmmm") // v8
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// Three registers of different lengths
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INST(asimd_VADDL, "VADDL/VADDW", "1111001U1Dzznnnndddd000oN0M0mmmm") // ASIMD
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@ -877,6 +877,7 @@ struct TranslatorVisitor final {
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bool asimd_VRSQRTS(bool D, bool sz, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm);
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bool v8_SHA256H(bool D, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm);
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bool v8_SHA256H2(bool D, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm);
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bool v8_SHA256SU1(bool D, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm);
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// Advanced SIMD three registers with different lengths
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bool asimd_VADDL(bool U, bool D, size_t sz, size_t Vn, size_t Vd, bool op, bool N, bool M, size_t Vm);
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@ -867,6 +867,24 @@ bool TranslatorVisitor::v8_SHA256H2(bool D, size_t Vn, size_t Vd, bool N, bool Q
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return true;
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}
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bool TranslatorVisitor::v8_SHA256SU1(bool D, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm) {
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if (!Q || Common::Bit<0>(Vd) || Common::Bit<0>(Vn) || Common::Bit<0>(Vm)) {
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return UndefinedInstruction();
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}
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const auto d = ToVector(Q, Vd, D);
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const auto n = ToVector(Q, Vn, N);
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const auto m = ToVector(Q, Vm, M);
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const auto x = ir.GetVector(d);
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const auto y = ir.GetVector(n);
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const auto z = ir.GetVector(m);
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const auto result = ir.SHA256MessageSchedule1(x, y, z);
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ir.SetVector(d, result);
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return true;
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}
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// ASIMD Three registers of different length
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bool TranslatorVisitor::asimd_VADDL(bool U, bool D, size_t sz, size_t Vn, size_t Vd, bool op, bool N, bool M, size_t Vm) {
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