From dfb318f2088d110d802d5e4425b3c331b8e2d374 Mon Sep 17 00:00:00 2001 From: bunnei Date: Thu, 4 Aug 2016 22:47:27 -0400 Subject: [PATCH] arm: Implement STRD reg/imm instructions. --- src/frontend/decoder/arm.h | 4 ++-- .../translate/translate_arm/load_store.cpp | 24 +++++++++++++++++-- 2 files changed, 24 insertions(+), 4 deletions(-) diff --git a/src/frontend/decoder/arm.h b/src/frontend/decoder/arm.h index ff255c9c..95802411 100644 --- a/src/frontend/decoder/arm.h +++ b/src/frontend/decoder/arm.h @@ -205,8 +205,8 @@ boost::optional&> DecodeArm(u32 instruction) { INST(&V::arm_STRB_reg, "STRB (reg)", "cccc011pu1w0nnnnddddvvvvvrr0mmmm"), //INST(&V::arm_STRBT, "STRBT (A1)", "cccc0100u110nnnnttttvvvvvvvvvvvv"), //INST(&V::arm_STRBT, "STRBT (A2)", "cccc0110u110nnnnttttvvvvvrr0mmmm"), - //INST(&V::arm_STRD_imm, "STRD (imm)", "cccc000pu1w0nnnnddddvvvv1111vvvv"), // v5E - //INST(&V::arm_STRD_reg, "STRD (reg)", "cccc000pu0w0nnnndddd00001111mmmm"), // v5E + INST(&V::arm_STRD_imm, "STRD (imm)", "cccc000pu1w0nnnnddddvvvv1111vvvv"), // v5E + INST(&V::arm_STRD_reg, "STRD (reg)", "cccc000pu0w0nnnndddd00001111mmmm"), // v5E INST(&V::arm_STRH_imm, "STRH (imm)", "cccc000pu1w0nnnnddddvvvv1011vvvv"), INST(&V::arm_STRH_reg, "STRH (reg)", "cccc000pu0w0nnnndddd00001011mmmm"), //INST(&V::arm_STRHT, "STRHT (A1)", "----0000-110------------1011----"), diff --git a/src/frontend/translate/translate_arm/load_store.cpp b/src/frontend/translate/translate_arm/load_store.cpp index e037ad0a..898d2f90 100644 --- a/src/frontend/translate/translate_arm/load_store.cpp +++ b/src/frontend/translate/translate_arm/load_store.cpp @@ -176,11 +176,31 @@ bool ArmTranslatorVisitor::arm_STRBT() { } bool ArmTranslatorVisitor::arm_STRD_imm(Cond cond, bool P, bool U, bool W, Reg n, Reg d, Imm4 imm8a, Imm4 imm8b) { - return InterpretThisInstruction(); + if (ConditionPassed(cond)) { + const auto address_a = GetAddressingMode(ir, P, U, W, n, ir.Imm32(imm8a << 4 | imm8b)); + const auto address_b = ir.Add(address_a, ir.Imm32(4)); + const auto value_a = (d == Reg::PC) ? ir.Imm32(ir.PC() - 8) : ir.GetRegister(d); + const Reg reg_b = static_cast(std::min(d + 1, Reg::R15)); + const auto value_b = (reg_b == Reg::PC) ? ir.Imm32(ir.PC() - 8) : ir.GetRegister(reg_b); + ir.WriteMemory32(address_a, value_a); + ir.WriteMemory32(address_b, value_b); + } + + return true; } bool ArmTranslatorVisitor::arm_STRD_reg(Cond cond, bool P, bool U, bool W, Reg n, Reg d, Reg m) { - return InterpretThisInstruction(); + if (ConditionPassed(cond)) { + const auto address_a = GetAddressingMode(ir, P, U, W, n, ir.GetRegister(m)); + const auto address_b = ir.Add(address_a, ir.Imm32(4)); + const auto value_a = (d == Reg::PC) ? ir.Imm32(ir.PC() - 8) : ir.GetRegister(d); + const Reg reg_b = static_cast(std::min(d + 1, Reg::R15)); + const auto value_b = (reg_b == Reg::PC) ? ir.Imm32(ir.PC() - 8) : ir.GetRegister(reg_b); + ir.WriteMemory32(address_a, value_a); + ir.WriteMemory32(address_b, value_b); + } + + return true; } bool ArmTranslatorVisitor::arm_STRH_imm(Cond cond, bool P, bool U, bool W, Reg n, Reg d, Imm4 imm8a, Imm4 imm8b) {