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translate_arm/branch: Invert conditionals where applicable

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Allows unindenting code a bit.
This commit is contained in:
Lioncash 2019-02-28 23:34:57 -05:00 committed by MerryMage
parent 20fabc5083
commit df5c51ff47
1 changed files with 59 additions and 49 deletions
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108
src/frontend/A32/translate/translate_arm/branch.cpp
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@ -10,65 +10,75 @@
namespace Dynarmic::A32 {
// B <label>
bool ArmTranslatorVisitor::arm_B(Cond cond, Imm24 imm24) {
u32 imm32 = Common::SignExtend<26, u32>(imm24 << 2) + 8;
// B <label>
if (ConditionPassed(cond)) {
auto new_location = ir.current_location.AdvancePC(imm32);
ir.SetTerm(IR::Term::LinkBlock{ new_location });
return false;
if (!ConditionPassed(cond)) {
return true;
}
return true;
}
bool ArmTranslatorVisitor::arm_BL(Cond cond, Imm24 imm24) {
u32 imm32 = Common::SignExtend<26, u32>(imm24 << 2) + 8;
// BL <label>
if (ConditionPassed(cond)) {
ir.PushRSB(ir.current_location.AdvancePC(4));
ir.SetRegister(Reg::LR, ir.Imm32(ir.current_location.PC() + 4));
auto new_location = ir.current_location.AdvancePC(imm32);
ir.SetTerm(IR::Term::LinkBlock{ new_location });
return false;
}
return true;
}
bool ArmTranslatorVisitor::arm_BLX_imm(bool H, Imm24 imm24) {
u32 imm32 = Common::SignExtend<26, u32>((imm24 << 2)) + (H ? 2 : 0) + 8;
// BLX <label>
ir.PushRSB(ir.current_location.AdvancePC(4));
ir.SetRegister(Reg::LR, ir.Imm32(ir.current_location.PC() + 4));
auto new_location = ir.current_location.AdvancePC(imm32).SetTFlag(true);
ir.SetTerm(IR::Term::LinkBlock{ new_location });
const u32 imm32 = Common::SignExtend<26, u32>(imm24 << 2) + 8;
const auto new_location = ir.current_location.AdvancePC(imm32);
ir.SetTerm(IR::Term::LinkBlock{new_location});
return false;
}
bool ArmTranslatorVisitor::arm_BLX_reg(Cond cond, Reg m) {
if (m == Reg::PC)
return UnpredictableInstruction();
// BLX <Rm>
if (ConditionPassed(cond)) {
ir.PushRSB(ir.current_location.AdvancePC(4));
ir.BXWritePC(ir.GetRegister(m));
ir.SetRegister(Reg::LR, ir.Imm32(ir.current_location.PC() + 4));
ir.SetTerm(IR::Term::FastDispatchHint{});
return false;
// BL <label>
bool ArmTranslatorVisitor::arm_BL(Cond cond, Imm24 imm24) {
if (!ConditionPassed(cond)) {
return true;
}
return true;
ir.PushRSB(ir.current_location.AdvancePC(4));
ir.SetRegister(Reg::LR, ir.Imm32(ir.current_location.PC() + 4));
const u32 imm32 = Common::SignExtend<26, u32>(imm24 << 2) + 8;
const auto new_location = ir.current_location.AdvancePC(imm32);
ir.SetTerm(IR::Term::LinkBlock{new_location});
return false;
}
bool ArmTranslatorVisitor::arm_BX(Cond cond, Reg m) {
// BX <Rm>
if (ConditionPassed(cond)) {
ir.BXWritePC(ir.GetRegister(m));
if (m == Reg::R14)
ir.SetTerm(IR::Term::PopRSBHint{});
else
ir.SetTerm(IR::Term::FastDispatchHint{});
return false;
// BLX <label>
bool ArmTranslatorVisitor::arm_BLX_imm(bool H, Imm24 imm24) {
ir.PushRSB(ir.current_location.AdvancePC(4));
ir.SetRegister(Reg::LR, ir.Imm32(ir.current_location.PC() + 4));
const u32 imm32 = Common::SignExtend<26, u32>((imm24 << 2)) + (H ? 2 : 0) + 8;
const auto new_location = ir.current_location.AdvancePC(imm32).SetTFlag(true);
ir.SetTerm(IR::Term::LinkBlock{new_location});
return false;
}
// BLX <Rm>
bool ArmTranslatorVisitor::arm_BLX_reg(Cond cond, Reg m) {
if (m == Reg::PC) {
return UnpredictableInstruction();
}
return true;
if (!ConditionPassed(cond)) {
return true;
}
ir.PushRSB(ir.current_location.AdvancePC(4));
ir.BXWritePC(ir.GetRegister(m));
ir.SetRegister(Reg::LR, ir.Imm32(ir.current_location.PC() + 4));
ir.SetTerm(IR::Term::FastDispatchHint{});
return false;
}
// BX <Rm>
bool ArmTranslatorVisitor::arm_BX(Cond cond, Reg m) {
if (!ConditionPassed(cond)) {
return true;
}
ir.BXWritePC(ir.GetRegister(m));
if (m == Reg::R14) {
ir.SetTerm(IR::Term::PopRSBHint{});
} else {
ir.SetTerm(IR::Term::FastDispatchHint{});
}
return false;
}
bool ArmTranslatorVisitor::arm_BXJ(Cond cond, Reg m) {