Implement thumb1_EOR_reg

This commit is contained in:
MerryMage 2016-07-08 18:14:50 +08:00
parent 8a0511d297
commit df0c324923
8 changed files with 32 additions and 2 deletions

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@ -445,6 +445,15 @@ void EmitX64::EmitAnd(IR::Value* value_) {
code->AND(32, R(result), R(andend));
}
void EmitX64::EmitEor(IR::Value* value_) {
auto value = reinterpret_cast<IR::Inst*>(value_);
X64Reg eorend = reg_alloc.UseRegister(value->GetArg(1).get());
X64Reg result = reg_alloc.UseDefRegister(value->GetArg(0).get(), value);
code->XOR(32, R(result), R(eorend));
}
void EmitX64::EmitAddCycles(size_t cycles) {
ASSERT(cycles < std::numeric_limits<u32>::max());
code->SUB(64, MDisp(R15, offsetof(JitState, cycles_remaining)), Imm32(static_cast<u32>(cycles)));

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@ -54,6 +54,7 @@ public:
void EmitArithmeticShiftRight(IR::Value* value);
void EmitAddWithCarry(IR::Value* value);
void EmitAnd(IR::Value* value);
void EmitEor(IR::Value* value);
void EmitAddCycles(size_t cycles);

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@ -56,7 +56,7 @@ private:
};
template <typename V>
static const std::array<Thumb1Matcher<V>, 10> g_thumb1_instruction_table {{
static const std::array<Thumb1Matcher<V>, 11> g_thumb1_instruction_table {{
#define INST(fn, name, bitstring) detail::detail<Thumb1Matcher, u16, 16>::GetMatcher<decltype(fn), fn>(name, bitstring)
@ -75,7 +75,7 @@ static const std::array<Thumb1Matcher<V>, 10> g_thumb1_instruction_table {{
// Data-processing instructions
{ INST(&V::thumb1_AND_reg, "AND (reg)", "0100000000mmmddd") },
// { INST(&V::thumb1_EOR_reg, "EOR (reg)", "0100000001mmmddd") },
{ INST(&V::thumb1_EOR_reg, "EOR (reg)", "0100000001mmmddd") },
{ INST(&V::thumb1_LSL_reg, "LSL (reg)", "0100000010mmmddd") },
{ INST(&V::thumb1_LSR_reg, "LSR (reg)", "0100000011mmmddd") },
{ INST(&V::thumb1_ASR_reg, "ASR (reg)", "0100000100mmmddd") },

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@ -122,6 +122,10 @@ public:
return Common::StringFromFormat("ands %s, %s", RegStr(d_n), RegStr(m));
}
std::string thumb1_EOR_reg(Reg m, Reg d_n) {
return Common::StringFromFormat("eors %s, %s", RegStr(d_n), RegStr(m));
}
std::string thumb1_LSL_reg(Reg m, Reg d_n) {
return Common::StringFromFormat("lsls %s, %s", RegStr(d_n), RegStr(m));
}

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@ -31,3 +31,4 @@ OPCODE(LogicalShiftRight, T::U32, T::U32, T::U8,
OPCODE(ArithmeticShiftRight, T::U32, T::U32, T::U8, T::U1 )
OPCODE(AddWithCarry, T::U32, T::U32, T::U32, T::U1 )
OPCODE(And, T::U32, T::U32, T::U32 )
OPCODE(Eor, T::U32, T::U32, T::U32 )

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@ -110,6 +110,10 @@ IR::ValuePtr IREmitter::And(IR::ValuePtr a, IR::ValuePtr b) {
return Inst(IR::Opcode::And, {a, b});
}
IR::ValuePtr IREmitter::Eor(IR::ValuePtr a, IR::ValuePtr b) {
return Inst(IR::Opcode::Eor, {a, b});
}
void IREmitter::SetTerm(const IR::Terminal& terminal) {
ASSERT_MSG(block.terminal.which() == 0, "Terminal has already been set.");
block.terminal = terminal;

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@ -57,6 +57,7 @@ public:
ResultAndCarry ArithmeticShiftRight(IR::ValuePtr value_in, IR::ValuePtr shift_amount, IR::ValuePtr carry_in);
ResultAndCarryAndOverflow AddWithCarry(IR::ValuePtr a, IR::ValuePtr b, IR::ValuePtr carry_in);
IR::ValuePtr And(IR::ValuePtr a, IR::ValuePtr b);
IR::ValuePtr Eor(IR::ValuePtr a, IR::ValuePtr b);
void SetTerm(const IR::Terminal& terminal);

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@ -86,6 +86,16 @@ struct TranslatorVisitor final {
ir.SetZFlag(ir.IsZero(result));
return true;
}
bool thumb1_EOR_reg(Reg m, Reg d_n) {
const Reg d = d_n, n = d_n;
// EORS <Rdn>, <Rm>
// Note that it is not possible to encode Rdn == R15.
auto result = ir.Eor(ir.GetRegister(n), ir.GetRegister(m));
ir.SetRegister(d, result);
ir.SetNFlag(ir.MostSignificantBit(result));
ir.SetZFlag(ir.IsZero(result));
return true;
}
bool thumb1_LSL_reg(Reg m, Reg d_n) {
const Reg d = d_n, n = d_n;
// LSLS <Rdn>, <Rm>