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A64: Implement SQABS' scalar variant

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Lioncash 2018-09-05 15:59:51 -04:00 committed by MerryMage
parent bda5d14c7f
commit db24e1f09b
2 changed files with 11 additions and 1 deletions
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2
src/frontend/A64/decoder/a64.inc
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@ -407,7 +407,7 @@ INST(FRSQRTE_2, "FRSQRTE", "01111
// Data Processing - FP and SIMD - Scalar two-register misc
//INST(SUQADD_1, "SUQADD", "01011110zz100000001110nnnnnddddd")
//INST(SQABS_1, "SQABS", "01011110zz100000011110nnnnnddddd")
INST(SQABS_1, "SQABS", "01011110zz100000011110nnnnnddddd")
INST(CMGT_zero_1, "CMGT (zero)", "01011110zz100000100010nnnnnddddd")
INST(CMEQ_zero_1, "CMEQ (zero)", "01011110zz100000100110nnnnnddddd")
INST(CMLT_1, "CMLT (zero)", "01011110zz100000101010nnnnnddddd")

10
src/frontend/A64/translate/impl/simd_scalar_two_register_misc.cpp
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@ -205,6 +205,16 @@ bool TranslatorVisitor::SCVTF_int_2(bool sz, Vec Vn, Vec Vd) {
return true;
}
bool TranslatorVisitor::SQABS_1(Imm<2> size, Vec Vn, Vec Vd) {
const size_t esize = 8 << size.ZeroExtend();
const IR::U128 operand = ir.ZeroExtendToQuad(ir.VectorGetElement(esize, V(128, Vn), 0));
const IR::U128 result = ir.VectorSignedSaturatedAbs(esize, operand);
V(128, Vd, result);
return true;
}
bool TranslatorVisitor::SQXTN_1(Imm<2> size, Vec Vn, Vec Vd) {
return SaturatedNarrow(*this, size, Vn, Vd, &IREmitter::VectorSignedSaturatedNarrowToSigned);
}