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VFP: Implement VABS

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This commit is contained in:
MerryMage 2016-08-07 01:27:18 +01:00
parent f88b1b4c2e
commit ce6b5f8210
10 changed files with 59 additions and 1 deletions
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16
src/backend_x64/emit_x64.cpp
View file

@ -1090,6 +1090,22 @@ static void DefaultNaN64(XEmitter* code, Routines* routines, X64Reg xmm_value) {
code->SetJumpTarget(fixup);
}
void EmitX64::EmitFPAbs32(IR::Block& block, IR::Inst* inst) {
IR::Value a = inst->GetArg(0);
X64Reg result = reg_alloc.UseDefRegister(a, inst, any_xmm);
code->PAND(result, routines->MFloatNonSignMask32());
}
void EmitX64::EmitFPAbs64(IR::Block& block, IR::Inst* inst) {
IR::Value a = inst->GetArg(0);
X64Reg result = reg_alloc.UseDefRegister(a, inst, any_xmm);
code->PAND(result, routines->MFloatNonSignMask64());
}
void EmitX64::EmitFPAdd32(IR::Block& block, IR::Inst* inst) {
IR::Value a = inst->GetArg(0);
IR::Value b = inst->GetArg(1);

2
src/backend_x64/routines.cpp
View file

@ -36,6 +36,8 @@ void Routines::GenConstants() {
Write32(0x80000000u);
const_FloatNaN32 = AlignCode16();
Write32(0x7fc00000u);
const_FloatNonSignMask32 = AlignCode16();
Write64(0x7fffffffu);
const_FloatNegativeZero64 = AlignCode16();
Write64(0x8000000000000000u);
const_FloatNaN64 = AlignCode16();

4
src/backend_x64/routines.h
View file

@ -25,6 +25,9 @@ public:
Gen::OpArg MFloatNaN32() const {
return Gen::M(const_FloatNaN32);
}
Gen::OpArg MFloatNonSignMask32() const {
return Gen::M(const_FloatNonSignMask32);
}
Gen::OpArg MFloatNegativeZero64() const {
return Gen::M(const_FloatNegativeZero64);
}
@ -41,6 +44,7 @@ public:
private:
const u8* const_FloatNegativeZero32;
const u8* const_FloatNaN32;
const u8* const_FloatNonSignMask32;
const u8* const_FloatNegativeZero64;
const u8* const_FloatNaN64;
const u8* const_FloatNonSignMask64;

2
src/frontend/decoder/vfp2.h
View file

@ -77,7 +77,7 @@ boost::optional<const VFP2Matcher<V>&> DecodeVFP2(u32 instruction) {
// Floating-point other instructions
// VMOV_imm
// VMOV_reg
// VABS
INST(&V::vfp2_VABS, "VABS", "cccc11101D110000dddd101z11M0mmmm"),
// VNEG
// VSQRT
// VCMP

4
src/frontend/disassembler/disassembler_arm.cpp
View file

@ -563,6 +563,10 @@ public:
std::string vfp2_VADD(Cond cond, bool D, size_t Vn, size_t Vd, bool sz, bool N, bool M, size_t Vm) {
return Common::StringFromFormat("vadd%s.%s %s, %s, %s", CondToString(cond), sz ? "f64" : "f32", FPRegStr(sz, Vd, D).c_str(), FPRegStr(sz, Vn, N).c_str(), FPRegStr(sz, Vm, M).c_str());
}
std::string vfp2_VABS(Cond cond, bool D, size_t Vd, bool sz, bool M, size_t Vm) {
return Common::StringFromFormat("vadd%s.%s %s, %s", CondToString(cond), sz ? "f64" : "f32", FPRegStr(sz, Vd, D).c_str(), FPRegStr(sz, Vm, M).c_str());
}
};
std::string DisassembleArm(u32 instruction) {

8
src/frontend/ir/ir_emitter.cpp
View file

@ -274,6 +274,14 @@ IR::Value IREmitter::ByteReverseDual(const IR::Value& a) {
return Inst(IR::Opcode::ByteReverseDual, {a});
}
IR::Value IREmitter::FPAbs32(const IR::Value& a) {
return Inst(IR::Opcode::FPAbs32, {a});
}
IR::Value IREmitter::FPAbs64(const IR::Value& a) {
return Inst(IR::Opcode::FPAbs64, {a});
}
IR::Value IREmitter::FPAdd32(const IR::Value& a, const IR::Value& b, bool fpscr_controlled) {
ASSERT(fpscr_controlled);
return Inst(IR::Opcode::FPAdd32, {a, b});

2
src/frontend/ir/ir_emitter.h
View file

@ -92,6 +92,8 @@ public:
IR::Value ByteReverseHalf(const IR::Value& a);
IR::Value ByteReverseDual(const IR::Value& a);
IR::Value FPAbs32(const IR::Value& a);
IR::Value FPAbs64(const IR::Value& a);
IR::Value FPAdd32(const IR::Value& a, const IR::Value& b, bool fpscr_controlled);
IR::Value FPAdd64(const IR::Value& a, const IR::Value& b, bool fpscr_controlled);

2
src/frontend/ir/opcodes.inc
View file

@ -60,6 +60,8 @@ OPCODE(ByteReverseHalf, T::U16, T::U16
OPCODE(ByteReverseDual, T::U64, T::U64 )
// Floating-point
OPCODE(FPAbs32, T::F32, T::F32 )
OPCODE(FPAbs64, T::F64, T::F64 )
OPCODE(FPAdd32, T::F32, T::F32, T::F32 )
OPCODE(FPAdd64, T::F64, T::F64, T::F64 )

3
src/frontend/translate/translate_arm/translate_arm.h
View file

@ -320,6 +320,9 @@ struct ArmTranslatorVisitor final {
// Floating-point three-register data processing instructions
bool vfp2_VADD(Cond cond, bool D, size_t Vn, size_t Vd, bool sz, bool N, bool M, size_t Vm);
// Floating-point misc instructions
bool vfp2_VABS(Cond cond, bool D, size_t Vd, bool sz, bool M, size_t Vm);
};
} // namespace Arm

17
src/frontend/translate/translate_arm/vfp2.cpp
View file

@ -36,5 +36,22 @@ bool ArmTranslatorVisitor::vfp2_VADD(Cond cond, bool D, size_t Vn, size_t Vd, bo
return true;
}
bool ArmTranslatorVisitor::vfp2_VABS(Cond cond, bool D, size_t Vd, bool sz, bool M, size_t Vm) {
if (ir.current_location.FPSCR_Len() != 1 || ir.current_location.FPSCR_Stride() != 1)
return InterpretThisInstruction(); // TODO: Vectorised floating point instructions
ExtReg d = ToExtReg(sz, Vd, D);
ExtReg m = ToExtReg(sz, Vm, M);
// VABS.{F32,F64} <{S,D}d>, <{S,D}m>
if (ConditionPassed(cond)) {
auto a = ir.GetExtendedRegister(m);
auto result = sz
? ir.FPAbs64(a)
: ir.FPAbs32(a);
ir.SetExtendedRegister(d, result);
}
return true;
}
} // namespace Arm
} // namespace Dynarmic