diff --git a/src/frontend/A32/decoder/thumb32.inc b/src/frontend/A32/decoder/thumb32.inc
index bf2bc56a..c41766a6 100644
--- a/src/frontend/A32/decoder/thumb32.inc
+++ b/src/frontend/A32/decoder/thumb32.inc
@@ -124,10 +124,10 @@ INST(thumb32_UDF,            "Invalid decoding",         "11110-111-------10-0--
 INST(thumb32_B_cond,         "B (cond)",                 "11110Sccccvvvvvv10i0ivvvvvvvvvvv")
 
 // Store Single Data Item
-//INST(thumb32_STRB_imm_1,     "STRB (imm)",               "111110000000--------1--1--------")
-//INST(thumb32_STRB_imm_2,     "STRB (imm)",               "111110000000--------1100--------")
-//INST(thumb32_STRB_imm_3,     "STRB (imm)",               "111110001000--------------------")
-//INST(thumb32_STRBT,          "STRBT",                    "111110000000--------1110--------")
+INST(thumb32_STRB_imm_1,     "STRB (imm)",               "111110000000nnnntttt1PU1iiiiiiii")
+INST(thumb32_STRB_imm_2,     "STRB (imm)",               "111110000000nnnntttt1100iiiiiiii")
+INST(thumb32_STRB_imm_3,     "STRB (imm)",               "111110001000nnnnttttiiiiiiiiiiii")
+INST(thumb32_STRBT,          "STRBT",                    "111110000000nnnntttt1110iiiiiiii")
 INST(thumb32_STRB,           "STRB (reg)",               "111110000000nnnntttt000000iimmmm")
 //INST(thumb32_STRH_imm_1,     "STRH (imm)",               "111110000010--------1--1--------")
 //INST(thumb32_STRH_imm_2,     "STRH (imm)",               "111110000010--------1100--------")
diff --git a/src/frontend/A32/translate/impl/thumb32_store_single_data_item.cpp b/src/frontend/A32/translate/impl/thumb32_store_single_data_item.cpp
index 0b776e75..3b5617f6 100644
--- a/src/frontend/A32/translate/impl/thumb32_store_single_data_item.cpp
+++ b/src/frontend/A32/translate/impl/thumb32_store_single_data_item.cpp
@@ -29,6 +29,80 @@ static bool StoreRegister(ThumbTranslatorVisitor& v, Reg n, Reg t, Imm<2> imm2,
     return true;
 }
 
+static bool StoreByteImmediate(ThumbTranslatorVisitor& v, Reg n, Reg t, bool P, bool U, bool W, Imm<8> imm8) {
+    const auto imm32 = imm8.ZeroExtend();
+    const auto reg_n = v.ir.GetRegister(n);
+    const auto reg_t = v.ir.GetRegister(t);
+
+    const IR::U32 offset_address = U ? v.ir.Add(reg_n, v.ir.Imm32(imm32))
+                                     : v.ir.Sub(reg_n, v.ir.Imm32(imm32));
+    const IR::U32 address = P ? offset_address
+                              : reg_n;
+    const IR::U8 data = v.ir.LeastSignificantByte(reg_t);
+
+    v.ir.WriteMemory8(address, data);
+    if (W) {
+        v.ir.SetRegister(n, offset_address);
+    }
+
+    return true;
+}
+
+bool ThumbTranslatorVisitor::thumb32_STRB_imm_1(Reg n, Reg t, bool P, bool U, Imm<8> imm8) {
+    if (n == Reg::PC) {
+        return UndefinedInstruction();
+    }
+    if (t == Reg::PC || n == t) {
+        return UnpredictableInstruction();
+    }
+    return StoreByteImmediate(*this, n, t, P, U, true, imm8);
+}
+
+bool ThumbTranslatorVisitor::thumb32_STRB_imm_2(Reg n, Reg t, Imm<8> imm8) {
+    if (n == Reg::PC) {
+        return UndefinedInstruction();
+    }
+    if (t == Reg::PC) {
+        return UnpredictableInstruction();
+    }
+    return StoreByteImmediate(*this, n, t, true, false, false, imm8);
+}
+
+bool ThumbTranslatorVisitor::thumb32_STRB_imm_3(Reg n, Reg t, Imm<12> imm12) {
+    if (n == Reg::PC) {
+        return UndefinedInstruction();
+    }
+    if (t == Reg::PC) {
+        return UnpredictableInstruction();
+    }
+
+    const auto imm32 = imm12.ZeroExtend();
+    const auto reg_n = ir.GetRegister(n);
+    const auto reg_t = ir.GetRegister(t);
+    const auto address = ir.Add(reg_n, ir.Imm32(imm32));
+    const auto data = ir.LeastSignificantByte(reg_t);
+
+    ir.WriteMemory8(address, data);
+    return true;
+}
+
+bool ThumbTranslatorVisitor::thumb32_STRBT(Reg n, Reg t, Imm<8> imm8) {
+    // TODO: Add an unpredictable instruction path if this
+    //       is executed in hypervisor mode if we ever support
+    //       privileged execution levels.
+
+    if (n == Reg::PC) {
+        return UndefinedInstruction();
+    }
+    if (t == Reg::PC) {
+        return UnpredictableInstruction();
+    }
+
+    // Treat this as a normal STRB, given we don't support
+    // execution levels other than EL0 currently.
+    return StoreByteImmediate(*this, n, t, true, true, false, imm8);
+}
+
 bool ThumbTranslatorVisitor::thumb32_STRB(Reg n, Reg t, Imm<2> imm2, Reg m) {
     return StoreRegister(*this, n, t, imm2, m, [this](const IR::U32& offset_address, const IR::U32& data) {
         ir.WriteMemory8(offset_address, ir.LeastSignificantByte(data));
diff --git a/src/frontend/A32/translate/impl/translate_thumb.h b/src/frontend/A32/translate/impl/translate_thumb.h
index d85942fd..6541842e 100644
--- a/src/frontend/A32/translate/impl/translate_thumb.h
+++ b/src/frontend/A32/translate/impl/translate_thumb.h
@@ -243,6 +243,10 @@ struct ThumbTranslatorVisitor final {
     bool thumb32_B_cond(Imm<1> S, Cond cond, Imm<6> hi, Imm<1> j1, Imm<1> j2, Imm<11> lo);
 
     // thumb32 store single data item instructions
+    bool thumb32_STRB_imm_1(Reg n, Reg t, bool P, bool U, Imm<8> imm8);
+    bool thumb32_STRB_imm_2(Reg n, Reg t, Imm<8> imm8);
+    bool thumb32_STRB_imm_3(Reg n, Reg t, Imm<12> imm12);
+    bool thumb32_STRBT(Reg n, Reg t, Imm<8> imm8);
     bool thumb32_STRB(Reg n, Reg t, Imm<2> imm2, Reg m);
     bool thumb32_STRH(Reg n, Reg t, Imm<2> imm2, Reg m);
     bool thumb32_STR_reg(Reg n, Reg t, Imm<2> imm2, Reg m);