From caab1bbc7c9e9921c08e5af84d45feccb53136ac Mon Sep 17 00:00:00 2001 From: bunnei Date: Thu, 4 Aug 2016 19:35:17 -0400 Subject: [PATCH] arm: Implement STR reg/imm instructions. --- src/frontend/decoder/arm.h | 4 ++-- .../translate/translate_arm/load_store.cpp | 15 +++++++++++++-- 2 files changed, 15 insertions(+), 4 deletions(-) diff --git a/src/frontend/decoder/arm.h b/src/frontend/decoder/arm.h index 72de5e93..3e586e5f 100644 --- a/src/frontend/decoder/arm.h +++ b/src/frontend/decoder/arm.h @@ -199,8 +199,8 @@ boost::optional&> DecodeArm(u32 instruction) { //INST(&V::arm_LDRSHT, "LDRSHT (A2)", "----0000-011--------00001111----"), //INST(&V::arm_LDRT, "LDRT (A1)", "cccc0100u011nnnnttttvvvvvvvvvvvv"), //INST(&V::arm_LDRT, "LDRT (A2)", "cccc0110u011nnnnttttvvvvvrr0mmmm"), - //INST(&V::arm_STR_imm, "STR (imm)", "cccc010pu0w0nnnnddddvvvvvvvvvvvv"), - //INST(&V::arm_STR_reg, "STR (reg)", "cccc011pu0w0nnnnddddvvvvvrr0mmmm"), + INST(&V::arm_STR_imm, "STR (imm)", "cccc010pu0w0nnnnddddvvvvvvvvvvvv"), + INST(&V::arm_STR_reg, "STR (reg)", "cccc011pu0w0nnnnddddvvvvvrr0mmmm"), //INST(&V::arm_STRB_imm, "STRB (imm)", "cccc010pu1w0nnnnddddvvvvvvvvvvvv"), //INST(&V::arm_STRB_reg, "STRB (reg)", "cccc011pu1w0nnnnddddvvvvvrr0mmmm"), //INST(&V::arm_STRBT, "STRBT (A1)", "cccc0100u110nnnnttttvvvvvvvvvvvv"), diff --git a/src/frontend/translate/translate_arm/load_store.cpp b/src/frontend/translate/translate_arm/load_store.cpp index e5a600ce..6e61ed36 100644 --- a/src/frontend/translate/translate_arm/load_store.cpp +++ b/src/frontend/translate/translate_arm/load_store.cpp @@ -132,11 +132,22 @@ bool ArmTranslatorVisitor::arm_LDRT() { } bool ArmTranslatorVisitor::arm_STR_imm(Cond cond, bool P, bool U, bool W, Reg n, Reg d, Imm12 imm12) { - return InterpretThisInstruction(); + if (ConditionPassed(cond)) { + const auto address = GetAddressingMode(ir, P, U, W, n, ir.Imm32(imm12)); + ir.WriteMemory32(address, ir.GetRegister(d)); + } + + return true; } bool ArmTranslatorVisitor::arm_STR_reg(Cond cond, bool P, bool U, bool W, Reg n, Reg d, Imm5 imm5, ShiftType shift, Reg m) { - return InterpretThisInstruction(); + if (ConditionPassed(cond)) { + const auto shifted = EmitImmShift(ir.GetRegister(m), shift, imm5, ir.GetCFlag()); + const auto address = GetAddressingMode(ir, P, U, W, n, shifted.result); + ir.WriteMemory32(address, ir.GetRegister(d)); + } + + return true; } bool ArmTranslatorVisitor::arm_STRB_imm(Cond cond, bool P, bool U, bool W, Reg n, Reg d, Imm12 imm12) {