From c97efcb978f7093cda530bd5b403eef04e779e4c Mon Sep 17 00:00:00 2001 From: Lioncash Date: Sat, 23 Mar 2019 13:21:55 -0400 Subject: [PATCH] frontend/ir_emitter: Add half-precision variant of FPNeg --- src/backend/x64/emit_x64_floating_point.cpp | 15 +++++++++++++-- src/frontend/ir/ir_emitter.cpp | 12 +++++++++--- src/frontend/ir/ir_emitter.h | 2 +- src/frontend/ir/opcodes.inc | 1 + 4 files changed, 24 insertions(+), 6 deletions(-) diff --git a/src/backend/x64/emit_x64_floating_point.cpp b/src/backend/x64/emit_x64_floating_point.cpp index 028c281d..b06a9eeb 100644 --- a/src/backend/x64/emit_x64_floating_point.cpp +++ b/src/backend/x64/emit_x64_floating_point.cpp @@ -38,6 +38,8 @@ namespace { const Xbyak::Reg64 INVALID_REG = Xbyak::Reg64(-1); +constexpr u64 f16_negative_zero = 0x8000; + constexpr u64 f32_negative_zero = 0x80000000u; constexpr u64 f32_nan = 0x7fc00000u; constexpr u64 f32_non_sign_mask = 0x7fffffffu; @@ -341,9 +343,18 @@ void EmitX64::EmitFPAbs64(EmitContext& ctx, IR::Inst* inst) { ctx.reg_alloc.DefineValue(inst, result); } +void EmitX64::EmitFPNeg16(EmitContext& ctx, IR::Inst* inst) { + auto args = ctx.reg_alloc.GetArgumentInfo(inst); + const Xbyak::Xmm result = ctx.reg_alloc.UseScratchXmm(args[0]); + + code.pxor(result, code.MConst(xword, f16_negative_zero)); + + ctx.reg_alloc.DefineValue(inst, result); +} + void EmitX64::EmitFPNeg32(EmitContext& ctx, IR::Inst* inst) { auto args = ctx.reg_alloc.GetArgumentInfo(inst); - Xbyak::Xmm result = ctx.reg_alloc.UseScratchXmm(args[0]); + const Xbyak::Xmm result = ctx.reg_alloc.UseScratchXmm(args[0]); code.pxor(result, code.MConst(xword, f32_negative_zero)); @@ -352,7 +363,7 @@ void EmitX64::EmitFPNeg32(EmitContext& ctx, IR::Inst* inst) { void EmitX64::EmitFPNeg64(EmitContext& ctx, IR::Inst* inst) { auto args = ctx.reg_alloc.GetArgumentInfo(inst); - Xbyak::Xmm result = ctx.reg_alloc.UseScratchXmm(args[0]); + const Xbyak::Xmm result = ctx.reg_alloc.UseScratchXmm(args[0]); code.pxor(result, code.MConst(xword, f64_negative_zero)); diff --git a/src/frontend/ir/ir_emitter.cpp b/src/frontend/ir/ir_emitter.cpp index 35c8d07b..75eb7b86 100644 --- a/src/frontend/ir/ir_emitter.cpp +++ b/src/frontend/ir/ir_emitter.cpp @@ -1880,11 +1880,17 @@ U32U64 IREmitter::FPMulX(const U32U64& a, const U32U64& b) { } } -U32U64 IREmitter::FPNeg(const U32U64& a) { - if (a.GetType() == Type::U32) { +U16U32U64 IREmitter::FPNeg(const U16U32U64& a) { + switch (a.GetType()) { + case Type::U16: + return Inst(Opcode::FPNeg16, a); + case Type::U32: return Inst(Opcode::FPNeg32, a); - } else { + case Type::U64: return Inst(Opcode::FPNeg64, a); + default: + UNREACHABLE(); + return U16U32U64{}; } } diff --git a/src/frontend/ir/ir_emitter.h b/src/frontend/ir/ir_emitter.h index 0e29d716..fa33d21a 100644 --- a/src/frontend/ir/ir_emitter.h +++ b/src/frontend/ir/ir_emitter.h @@ -303,7 +303,7 @@ public: U32U64 FPMul(const U32U64& a, const U32U64& b, bool fpcr_controlled); U32U64 FPMulAdd(const U32U64& addend, const U32U64& op1, const U32U64& op2, bool fpcr_controlled); U32U64 FPMulX(const U32U64& a, const U32U64& b); - U32U64 FPNeg(const U32U64& a); + U16U32U64 FPNeg(const U16U32U64& a); U32U64 FPRecipEstimate(const U32U64& a); U16U32U64 FPRecipExponent(const U16U32U64& a); U32U64 FPRecipStepFused(const U32U64& a, const U32U64& b); diff --git a/src/frontend/ir/opcodes.inc b/src/frontend/ir/opcodes.inc index ca87994a..81205e13 100644 --- a/src/frontend/ir/opcodes.inc +++ b/src/frontend/ir/opcodes.inc @@ -482,6 +482,7 @@ OPCODE(FPMulAdd32, U32, U32, OPCODE(FPMulAdd64, U64, U64, U64, U64 ) OPCODE(FPMulX32, U32, U32, U32 ) OPCODE(FPMulX64, U64, U64, U64 ) +OPCODE(FPNeg16, U16, U16 ) OPCODE(FPNeg32, U32, U32 ) OPCODE(FPNeg64, U64, U64 ) OPCODE(FPRecipEstimate32, U32, U32 )