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translate_arm/misc: Invert conditionals where applicable

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Lioncash 2019-03-01 00:58:47 -05:00 committed by MerryMage
parent a7bf5ff77d
commit c8dad40d81
1 changed files with 19 additions and 10 deletions
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33
src/frontend/A32/translate/translate_arm/misc.cpp
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@ -8,26 +8,35 @@
namespace Dynarmic::A32 { namespace Dynarmic::A32 {
// CLZ<c> <Rd>, <Rm>
bool ArmTranslatorVisitor::arm_CLZ(Cond cond, Reg d, Reg m) { bool ArmTranslatorVisitor::arm_CLZ(Cond cond, Reg d, Reg m) {
if (d == Reg::PC || m == Reg::PC) if (d == Reg::PC || m == Reg::PC) {
return UnpredictableInstruction(); return UnpredictableInstruction();
if (ConditionPassed(cond)) {
ir.SetRegister(d, ir.CountLeadingZeros(ir.GetRegister(m)));
} }
if (!ConditionPassed(cond)) {
return true; return true;
} }
bool ArmTranslatorVisitor::arm_SEL(Cond cond, Reg n, Reg d, Reg m) { ir.SetRegister(d, ir.CountLeadingZeros(ir.GetRegister(m)));
if (n == Reg::PC || d == Reg::PC || m == Reg::PC) return true;
return UnpredictableInstruction();
if (ConditionPassed(cond)) {
auto to = ir.GetRegister(m);
auto from = ir.GetRegister(n);
auto result = ir.PackedSelect(ir.GetGEFlags(), to, from);
ir.SetRegister(d, result);
} }
// SEL<c> <Rd>, <Rn>, <Rm>
bool ArmTranslatorVisitor::arm_SEL(Cond cond, Reg n, Reg d, Reg m) {
if (n == Reg::PC || d == Reg::PC || m == Reg::PC) {
return UnpredictableInstruction();
}
if (!ConditionPassed(cond)) {
return true;
}
const auto to = ir.GetRegister(m);
const auto from = ir.GetRegister(n);
const auto result = ir.PackedSelect(ir.GetGEFlags(), to, from);
ir.SetRegister(d, result);
return true; return true;
} }