diff --git a/src/frontend/A32/translate/impl/asimd_load_store_structures.cpp b/src/frontend/A32/translate/impl/asimd_load_store_structures.cpp
index 9f13d0b2..541c24f2 100644
--- a/src/frontend/A32/translate/impl/asimd_load_store_structures.cpp
+++ b/src/frontend/A32/translate/impl/asimd_load_store_structures.cpp
@@ -12,9 +12,6 @@
 namespace Dynarmic::A32 {
 
 namespace {
-ExtReg ToExtReg(size_t base, bool bit) {
-    return ExtReg::D0 + (base + (bit ? 16 : 0));
-}
 
 std::optional<std::tuple<size_t, size_t, size_t>> DecodeType(Imm<4> type, size_t size, size_t align) {
     switch (type.ZeroExtend()) {
@@ -82,7 +79,7 @@ bool ArmTranslatorVisitor::v8_VST_multiple(bool D, Reg n, size_t Vd, Imm<4> type
     }
     const auto [nelem, regs, inc] = *decoded_type;
 
-    const ExtReg d = ToExtReg(Vd, D);
+    const ExtReg d = ToExtRegD(Vd, D);
     const size_t d_last = RegNumber(d) + inc * (nelem - 1);
     if (n == Reg::R15 || d_last + regs > 32) {
         return UnpredictableInstruction();
@@ -127,7 +124,7 @@ bool ArmTranslatorVisitor::v8_VLD_multiple(bool D, Reg n, size_t Vd, Imm<4> type
     }
     const auto [nelem, regs, inc] = *decoded_type;
 
-    const ExtReg d = ToExtReg(Vd, D);
+    const ExtReg d = ToExtRegD(Vd, D);
     const size_t d_last = RegNumber(d) + inc * (nelem - 1);
     if (n == Reg::R15 || d_last + regs > 32) {
         return UnpredictableInstruction();
diff --git a/src/frontend/A32/translate/impl/asimd_one_reg_modified_immediate.cpp b/src/frontend/A32/translate/impl/asimd_one_reg_modified_immediate.cpp
index 4922a9aa..18116c0a 100644
--- a/src/frontend/A32/translate/impl/asimd_one_reg_modified_immediate.cpp
+++ b/src/frontend/A32/translate/impl/asimd_one_reg_modified_immediate.cpp
@@ -9,11 +9,6 @@
 #include "frontend/A32/translate/impl/translate_arm.h"
 
 namespace Dynarmic::A32 {
-namespace {
-ExtReg ToExtRegD(size_t base, bool bit) {
-    return ExtReg::D0 + (base + (bit ? 16 : 0));
-}
-} // Anonymous namespace
 
 bool ArmTranslatorVisitor::asimd_VMOV_imm(Imm<1> a, bool D, Imm<1> b, Imm<1> c, Imm<1> d, size_t Vd,
                                           Imm<4> cmode, bool Q, bool op, Imm<1> e, Imm<1> f, Imm<1> g, Imm<1> h) {
diff --git a/src/frontend/A32/translate/impl/asimd_three_same.cpp b/src/frontend/A32/translate/impl/asimd_three_same.cpp
index b0696dec..ab924f41 100644
--- a/src/frontend/A32/translate/impl/asimd_three_same.cpp
+++ b/src/frontend/A32/translate/impl/asimd_three_same.cpp
@@ -9,19 +9,15 @@
 
 namespace Dynarmic::A32 {
 namespace {
-ExtReg ToExtReg(size_t base, bool bit) {
-    return ExtReg::D0 + (base + (bit ? 16 : 0));
-}
-
 template <bool WithDst, typename Callable>
 bool BitwiseInstruction(ArmTranslatorVisitor& v, bool D, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm, Callable fn) {
     if (Q && (Common::Bit<0>(Vd) || Common::Bit<0>(Vn) || Common::Bit<0>(Vm))) {
         return v.UndefinedInstruction();
     }
 
-    const auto d = ToExtReg(Vd, D);
-    const auto m = ToExtReg(Vm, M);
-    const auto n = ToExtReg(Vn, N);
+    const auto d = ToExtRegD(Vd, D);
+    const auto m = ToExtRegD(Vm, M);
+    const auto n = ToExtRegD(Vn, N);
     const size_t regs = Q ? 2 : 1;
 
     for (size_t i = 0; i < regs; i++) {
diff --git a/src/frontend/A32/translate/impl/asimd_two_regs_misc.cpp b/src/frontend/A32/translate/impl/asimd_two_regs_misc.cpp
index f473b9b6..56f5b0c3 100644
--- a/src/frontend/A32/translate/impl/asimd_two_regs_misc.cpp
+++ b/src/frontend/A32/translate/impl/asimd_two_regs_misc.cpp
@@ -8,11 +8,6 @@
 #include "frontend/A32/translate/impl/translate_arm.h"
 
 namespace Dynarmic::A32 {
-namespace {
-ExtReg ToExtRegD(size_t base, bool bit) {
-    return ExtReg::D0 + (base + (bit ? 16 : 0));
-}
-} // Anonymous namespace
 
 bool ArmTranslatorVisitor::asimd_VSWP(bool D, size_t Vd, bool Q, bool M, size_t Vm) {
     if (Q && (Common::Bit<0>(Vd) || Common::Bit<0>(Vm))) {
diff --git a/src/frontend/A32/translate/impl/vfp.cpp b/src/frontend/A32/translate/impl/vfp.cpp
index 4bf6509a..3af21683 100644
--- a/src/frontend/A32/translate/impl/vfp.cpp
+++ b/src/frontend/A32/translate/impl/vfp.cpp
@@ -7,14 +7,6 @@
 
 namespace Dynarmic::A32 {
 
-static ExtReg ToExtReg(bool sz, size_t base, bool bit) {
-    if (sz) {
-        return static_cast<ExtReg>(static_cast<size_t>(ExtReg::D0) + base + (bit ? 16 : 0));
-    } else {
-        return static_cast<ExtReg>(static_cast<size_t>(ExtReg::S0) + (base << 1) + (bit ? 1 : 0));
-    }
-}
-
 template <typename FnT>
 bool ArmTranslatorVisitor::EmitVfpVectorOperation(bool sz, ExtReg d, ExtReg n, ExtReg m, const FnT& fn) {
     if (!ir.current_location.FPSCR().Stride()) {
diff --git a/src/frontend/A32/types.h b/src/frontend/A32/types.h
index ea6013ae..b47164a1 100644
--- a/src/frontend/A32/types.h
+++ b/src/frontend/A32/types.h
@@ -106,4 +106,20 @@ inline ExtReg operator+(ExtReg reg, size_t number) {
     return new_reg;
 }
 
+inline ExtReg ToExtRegD(size_t base, bool bit) {
+    return ExtReg::D0 + (base + (bit ? 16 : 0));
+}
+
+inline ExtReg ToExtRegS(size_t base, bool bit) {
+    return ExtReg::S0 + ((base << 1) + (bit ? 1 : 0));
+}
+
+inline ExtReg ToExtReg(bool sz, size_t base, bool bit) {
+    if (sz) {
+        return ToExtRegD(base, bit);
+    } else {
+        return ToExtRegS(base, bit);
+    }
+}
+
 } // namespace Dynarmic::A32