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A64: Implement UABD

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Lioncash 2018-04-02 11:25:26 -04:00 committed by MerryMage
parent ad5cf584ce
commit c2e7364d3e
2 changed files with 17 additions and 1 deletions
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2
src/frontend/A64/decoder/a64.inc
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@ -754,7 +754,7 @@ INST(USHL_2, "USHL", "0Q101
//INST(UQRSHL_2, "UQRSHL", "0Q101110zz1mmmmm010111nnnnnddddd")
INST(UMAX, "UMAX", "0Q101110zz1mmmmm011001nnnnnddddd")
INST(UMIN, "UMIN", "0Q101110zz1mmmmm011011nnnnnddddd")
//INST(UABD, "UABD", "0Q101110zz1mmmmm011101nnnnnddddd")
INST(UABD, "UABD", "0Q101110zz1mmmmm011101nnnnnddddd")
//INST(UABA, "UABA", "0Q101110zz1mmmmm011111nnnnnddddd")
INST(SUB_2, "SUB (vector)", "0Q101110zz1mmmmm100001nnnnnddddd")
INST(CMEQ_reg_2, "CMEQ (register)", "0Q101110zz1mmmmm100011nnnnnddddd")

16
src/frontend/A64/translate/impl/simd_three_same.cpp
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@ -227,6 +227,22 @@ bool TranslatorVisitor::UMAX(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
return true;
}
bool TranslatorVisitor::UABD(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
if (size == 0b11) {
return ReservedValue();
}
const size_t datasize = Q ? 128 : 64;
const size_t esize = 8 << size.ZeroExtend();
const IR::U128 operand1 = V(datasize, Vn);
const IR::U128 operand2 = V(datasize, Vm);
const IR::U128 result = ir.VectorUnsignedAbsoluteDifference(esize, operand1, operand2);
V(datasize, Vd, result);
return true;
}
bool TranslatorVisitor::UMIN(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
if (size == 0b11) {
return ReservedValue();