diff --git a/src/frontend/A64/decoder/a64.inc b/src/frontend/A64/decoder/a64.inc
index 204cb12a..bf32a974 100644
--- a/src/frontend/A64/decoder/a64.inc
+++ b/src/frontend/A64/decoder/a64.inc
@@ -580,7 +580,7 @@ INST(CMLT_2,                 "CMLT (zero)",                               "0Q001
 INST(ABS_2,                  "ABS",                                       "0Q001110zz100000101110nnnnnddddd")
 INST(XTN,                    "XTN, XTN2",                                 "0Q001110zz100001001010nnnnnddddd")
 INST(SQXTN_2,                "SQXTN, SQXTN2",                             "0Q001110zz100001010010nnnnnddddd")
-//INST(FCVTN,                  "FCVTN, FCVTN2",                             "0Q0011100z100001011010nnnnnddddd")
+INST(FCVTN,                  "FCVTN, FCVTN2",                             "0Q0011100z100001011010nnnnnddddd")
 INST(FCVTL,                  "FCVTL, FCVTL2",                             "0Q0011100z100001011110nnnnnddddd")
 //INST(FRINTN_1,               "FRINTN (vector)",                           "0Q00111001111001100010nnnnnddddd")
 INST(FRINTN_2,               "FRINTN (vector)",                           "0Q0011100z100001100010nnnnnddddd")
diff --git a/src/frontend/A64/translate/impl/simd_two_register_misc.cpp b/src/frontend/A64/translate/impl/simd_two_register_misc.cpp
index be02db13..130e5d13 100644
--- a/src/frontend/A64/translate/impl/simd_two_register_misc.cpp
+++ b/src/frontend/A64/translate/impl/simd_two_register_misc.cpp
@@ -286,6 +286,25 @@ bool TranslatorVisitor::FCVTL(bool Q, bool sz, Vec Vn, Vec Vd) {
     return true;
 }
 
+bool TranslatorVisitor::FCVTN(bool Q, bool sz, Vec Vn, Vec Vd) {
+    // Half-precision not handled directly.
+    if (!sz) {
+        return InterpretThisInstruction();
+    }
+
+    const IR::U128 operand = V(128, Vn);
+    IR::U128 result = ir.ZeroVector();
+
+    for (size_t i = 0; i < 2; i++) {
+        const IR::U32 element = ir.FPDoubleToSingle(ir.VectorGetElement(64, operand, i), true);
+
+        result = ir.VectorSetElement(32, result, i, element);
+    }
+
+    Vpart(64, Vd, Q, result);
+    return true;
+}
+
 bool TranslatorVisitor::FCVTNS_4(bool Q, bool sz, Vec Vn, Vec Vd) {
     return FloatConvertToInteger(*this, Q, sz, Vn, Vd, Signedness::Signed, FP::RoundingMode::ToNearest_TieEven);
 }