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A64: Implement ADDP (vector)

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This commit is contained in:
MerryMage 2018-01-23 17:44:34 +00:00
parent eaf545877a
commit b8e26bfdc3
2 changed files with 27 additions and 1 deletions
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2
src/frontend/A64/decoder/a64.inc
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@ -829,7 +829,7 @@ INST(ADD_vector, "ADD (vector)", "0Q001
//INST(MUL_vec, "MUL (vector)", "0Q001110zz1mmmmm100111nnnnnddddd") //INST(MUL_vec, "MUL (vector)", "0Q001110zz1mmmmm100111nnnnnddddd")
//INST(SMAXP, "SMAXP", "0Q001110zz1mmmmm101001nnnnnddddd") //INST(SMAXP, "SMAXP", "0Q001110zz1mmmmm101001nnnnnddddd")
//INST(SMINP, "SMINP", "0Q001110zz1mmmmm101011nnnnnddddd") //INST(SMINP, "SMINP", "0Q001110zz1mmmmm101011nnnnnddddd")
//INST(ADDP_vec, "ADDP (vector)", "0Q001110zz1mmmmm101111nnnnnddddd") INST(ADDP_vec, "ADDP (vector)", "0Q001110zz1mmmmm101111nnnnnddddd")
//INST(FMLAL_vec_1, "FMLAL, FMLAL2 (vector)", "0Q0011100z1mmmmm111011nnnnnddddd") //INST(FMLAL_vec_1, "FMLAL, FMLAL2 (vector)", "0Q0011100z1mmmmm111011nnnnnddddd")
//INST(FMLAL_vec_2, "FMLAL, FMLAL2 (vector)", "0Q1011100z1mmmmm110011nnnnnddddd") //INST(FMLAL_vec_2, "FMLAL, FMLAL2 (vector)", "0Q1011100z1mmmmm110011nnnnnddddd")
INST(AND_asimd, "AND (vector)", "0Q001110001mmmmm000111nnnnnddddd") INST(AND_asimd, "AND (vector)", "0Q001110001mmmmm000111nnnnnddddd")

26
src/frontend/A64/translate/impl/simd_three_same.cpp
View file

@ -35,6 +35,32 @@ bool TranslatorVisitor::ADD_vector(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd)
return true; return true;
} }
bool TranslatorVisitor::ADDP_vec(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
if (size == 0b11 && !Q) return ReservedValue();
const size_t esize = 8 << size.ZeroExtend<size_t>();
const size_t datasize = Q ? 128 : 64;
const IR::U128 operand1 = V(datasize, Vn);
const IR::U128 operand2 = V(datasize, Vm);
const IR::U128 result = [&]{
switch (esize) {
case 8:
return Q ? ir.VectorPairedAdd8(operand1, operand2) : ir.VectorLowerPairedAdd8(operand1, operand2);
case 16:
return Q ? ir.VectorPairedAdd16(operand1, operand2) : ir.VectorLowerPairedAdd16(operand1, operand2);
case 32:
return Q ? ir.VectorPairedAdd32(operand1, operand2) : ir.VectorLowerPairedAdd32(operand1, operand2);
default:
return ir.VectorPairedAdd64(operand1, operand2);
}
}();
V(datasize, Vd, result);
return true;
}
bool TranslatorVisitor::AND_asimd(bool Q, Vec Vm, Vec Vn, Vec Vd) { bool TranslatorVisitor::AND_asimd(bool Q, Vec Vm, Vec Vn, Vec Vd) {
const size_t datasize = Q ? 128 : 64; const size_t datasize = Q ? 128 : 64;