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A64: Implement FRSQRTS (scalar), single/double variant

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This commit is contained in:
MerryMage 2018-07-23 22:02:46 +01:00
parent 506e544bfe
commit b74d5520f9
2 changed files with 12 additions and 1 deletions
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2
src/frontend/A64/decoder/a64.inc
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@ -345,7 +345,7 @@ INST(FCMEQ_reg_2, "FCMEQ (register)", "01011
//INST(FRECPS_1, "FRECPS", "01011110010mmmmm001111nnnnnddddd")
//INST(FRECPS_2, "FRECPS", "010111100z1mmmmm111111nnnnnddddd")
//INST(FRSQRTS_1, "FRSQRTS", "01011110110mmmmm001111nnnnnddddd")
//INST(FRSQRTS_2, "FRSQRTS", "010111101z1mmmmm111111nnnnnddddd")
INST(FRSQRTS_2, "FRSQRTS", "010111101z1mmmmm111111nnnnnddddd")
//INST(FCMGE_reg_1, "FCMGE (register)", "01111110010mmmmm001001nnnnnddddd")
INST(FCMGE_reg_2, "FCMGE (register)", "011111100z1mmmmm111001nnnnnddddd")
//INST(FACGE_1, "FACGE", "01111110010mmmmm001011nnnnnddddd")

11
src/frontend/A64/translate/impl/simd_scalar_three_same.cpp
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@ -181,6 +181,17 @@ bool TranslatorVisitor::FABD_2(bool sz, Vec Vm, Vec Vn, Vec Vd) {
return true;
}
bool TranslatorVisitor::FRSQRTS_2(bool sz, Vec Vm, Vec Vn, Vec Vd) {
const size_t esize = sz ? 64 : 32;
const IR::U32U64 operand1 = V_scalar(esize, Vn);
const IR::U32U64 operand2 = V_scalar(esize, Vm);
const IR::U32U64 result = ir.FPRSqrtStepFused(operand1, operand2);
V_scalar(esize, Vd, result);
return true;
}
bool TranslatorVisitor::FACGE_2(bool sz, Vec Vm, Vec Vn, Vec Vd) {
return ScalarFPCompareRegister(*this, sz, Vm, Vn, Vd, FPComparisonType::AbsoluteGE);
}