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IR: Implement IR instructions A64{Get,Set}S

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This commit is contained in:
MerryMage 2018-01-26 18:35:19 +00:00
parent 16fa2cd8f6
commit b513b2ef05
6 changed files with 28 additions and 2 deletions
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9
src/backend_x64/a64_emit_x64.cpp
View file

@ -164,6 +164,15 @@ void A64EmitX64::EmitA64GetX(A64EmitContext& ctx, IR::Inst* inst) {
ctx.reg_alloc.DefineValue(inst, result);
}
void A64EmitX64::EmitA64GetS(A64EmitContext& ctx, IR::Inst* inst) {
A64::Vec vec = inst->GetArg(0).GetA64VecRef();
auto addr = qword[r15 + offsetof(A64JitState, vec) + sizeof(u64) * 2 * static_cast<size_t>(vec)];
Xbyak::Xmm result = ctx.reg_alloc.ScratchXmm();
code->movd(result, addr);
ctx.reg_alloc.DefineValue(inst, result);
}
void A64EmitX64::EmitA64GetD(A64EmitContext& ctx, IR::Inst* inst) {
A64::Vec vec = inst->GetArg(0).GetA64VecRef();
auto addr = qword[r15 + offsetof(A64JitState, vec) + sizeof(u64) * 2 * static_cast<size_t>(vec)];

8
src/frontend/A64/ir_emitter.cpp
View file

@ -93,6 +93,10 @@ IR::U64 IREmitter::GetX(Reg reg) {
return Inst<IR::U64>(Opcode::A64GetX, IR::Value(reg));
}
IR::U128 IREmitter::GetS(Vec vec) {
return Inst<IR::U128>(Opcode::A64GetS, IR::Value(vec));
}
IR::U128 IREmitter::GetD(Vec vec) {
return Inst<IR::U128>(Opcode::A64GetD, IR::Value(vec));
}
@ -117,6 +121,10 @@ void IREmitter::SetX(const Reg reg, const IR::U64& value) {
Inst(Opcode::A64SetX, IR::Value(reg), value);
}
void IREmitter::SetS(const Vec vec, const IR::U128& value) {
Inst(Opcode::A64SetS, IR::Value(vec), value);
}
void IREmitter::SetD(const Vec vec, const IR::U128& value) {
Inst(Opcode::A64SetD, IR::Value(vec), value);
}

2
src/frontend/A64/ir_emitter.h
View file

@ -52,11 +52,13 @@ public:
IR::U32 GetW(Reg source_reg);
IR::U64 GetX(Reg source_reg);
IR::U128 GetS(Vec source_vec);
IR::U128 GetD(Vec source_vec);
IR::U128 GetQ(Vec source_vec);
IR::U64 GetSP();
void SetW(Reg dest_reg, const IR::U32& value);
void SetX(Reg dest_reg, const IR::U64& value);
void SetS(Vec dest_vec, const IR::U128& value);
void SetD(Vec dest_vec, const IR::U128& value);
void SetQ(Vec dest_vec, const IR::U128& value);
void SetSP(const IR::U64& value);

5
src/frontend/A64/translate/impl/impl.cpp
View file

@ -124,6 +124,8 @@ void TranslatorVisitor::SP(size_t bitsize, IR::U32U64 value) {
IR::U128 TranslatorVisitor::V(size_t bitsize, Vec vec) {
switch (bitsize) {
case 32:
return ir.GetS(vec);
case 64:
return ir.GetD(vec);
case 128:
@ -135,6 +137,9 @@ IR::U128 TranslatorVisitor::V(size_t bitsize, Vec vec) {
void TranslatorVisitor::V(size_t bitsize, Vec vec, IR::U128 value) {
switch (bitsize) {
case 32:
ir.SetS(vec, value);
return;
case 64:
ir.SetD(vec, value);
return;

2
src/frontend/ir/microinstruction.cpp
View file

@ -150,6 +150,7 @@ bool Inst::ReadsFromCoreRegister() const {
case Opcode::A32GetExtendedRegister64:
case Opcode::A64GetW:
case Opcode::A64GetX:
case Opcode::A64GetS:
case Opcode::A64GetD:
case Opcode::A64GetQ:
case Opcode::A64GetSP:
@ -168,6 +169,7 @@ bool Inst::WritesToCoreRegister() const {
case Opcode::A32BXWritePC:
case Opcode::A64SetW:
case Opcode::A64SetX:
case Opcode::A64SetS:
case Opcode::A64SetD:
case Opcode::A64SetQ:
case Opcode::A64SetSP:

4
src/frontend/ir/opcodes.inc
View file

@ -42,7 +42,7 @@ A64OPC(GetW, T::U32, T::A64Reg
A64OPC(GetX, T::U64, T::A64Reg )
//A64OPC(GetB, T::U128, T::A64Vec )
//A64OPC(GetH, T::U128, T::A64Vec )
//A64OPC(GetS, T::U128, T::A64Vec )
A64OPC(GetS, T::U128, T::A64Vec )
A64OPC(GetD, T::U128, T::A64Vec )
A64OPC(GetQ, T::U128, T::A64Vec )
A64OPC(GetSP, T::U64, )
@ -50,7 +50,7 @@ A64OPC(SetW, T::Void, T::A64Reg, T::U32
A64OPC(SetX, T::Void, T::A64Reg, T::U64 )
//A64OPC(SetB, T::Void, T::A64Vec, T::U8 )
//A64OPC(SetH, T::Void, T::A64Vec, T::U16 )
//A64OPC(SetS, T::Void, T::A64Vec, T::U32 )
A64OPC(SetS, T::Void, T::A64Vec, T::U128 )
A64OPC(SetD, T::Void, T::A64Vec, T::U128 )
A64OPC(SetQ, T::Void, T::A64Vec, T::U128 )
A64OPC(SetSP, T::Void, T::U64 )