Tests: Tidy up ARM fuzz tests
This commit is contained in:
MerryMage
parent
328422b740
commit
b3bb1d5048
1 changed files with 244 additions and 240 deletions
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@ -167,8 +167,8 @@ public:
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return inst;
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}
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u32 Bits() { return bits; }
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u32 Mask() { return mask; }
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u32 Bits() const { return bits; }
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u32 Mask() const { return mask; }
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private:
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u32 bits = 0;
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u32 mask = 0;
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@ -432,8 +432,7 @@ TEST_CASE("VFP: VMOV (reg), VLDR", "[JitX64][vfp]") {
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}
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TEST_CASE("Fuzz ARM data processing instructions", "[JitX64]") {
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const std::array<InstructionGenerator, 16> imm_instructions = {
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{
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const std::array<InstructionGenerator, 16> imm_instructions = {{
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InstructionGenerator("cccc0010101Snnnnddddrrrrvvvvvvvv"),
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InstructionGenerator("cccc0010100Snnnnddddrrrrvvvvvvvv"),
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InstructionGenerator("cccc0010000Snnnnddddrrrrvvvvvvvv"),
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@ -450,11 +449,9 @@ TEST_CASE("Fuzz ARM data processing instructions", "[JitX64]") {
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InstructionGenerator("cccc0010010Snnnnddddrrrrvvvvvvvv"),
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InstructionGenerator("cccc00110011nnnn0000rrrrvvvvvvvv"),
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InstructionGenerator("cccc00110001nnnn0000rrrrvvvvvvvv"),
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}
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};
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}};
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const std::array<InstructionGenerator, 16> reg_instructions = {
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{
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const std::array<InstructionGenerator, 16> reg_instructions = {{
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InstructionGenerator("cccc0000101Snnnnddddvvvvvrr0mmmm"),
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InstructionGenerator("cccc0000100Snnnnddddvvvvvrr0mmmm"),
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InstructionGenerator("cccc0000000Snnnnddddvvvvvrr0mmmm"),
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@ -471,11 +468,9 @@ TEST_CASE("Fuzz ARM data processing instructions", "[JitX64]") {
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InstructionGenerator("cccc0000010Snnnnddddvvvvvrr0mmmm"),
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InstructionGenerator("cccc00010011nnnn0000vvvvvrr0mmmm"),
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InstructionGenerator("cccc00010001nnnn0000vvvvvrr0mmmm"),
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}
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};
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}};
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const std::array<InstructionGenerator, 16> rsr_instructions = {
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{
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const std::array<InstructionGenerator, 16> rsr_instructions = {{
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InstructionGenerator("cccc0000101Snnnnddddssss0rr1mmmm"),
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InstructionGenerator("cccc0000100Snnnnddddssss0rr1mmmm"),
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InstructionGenerator("cccc0000000Snnnnddddssss0rr1mmmm"),
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@ -492,8 +487,7 @@ TEST_CASE("Fuzz ARM data processing instructions", "[JitX64]") {
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InstructionGenerator("cccc0000010Snnnnddddssss0rr1mmmm"),
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InstructionGenerator("cccc00010011nnnn0000ssss0rr1mmmm"),
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InstructionGenerator("cccc00010001nnnn0000ssss0rr1mmmm"),
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}
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};
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}};
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auto instruction_select = [&](bool Rd_can_be_r15) -> auto {
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return [&, Rd_can_be_r15]() -> u32 {
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@ -560,6 +554,150 @@ TEST_CASE("Fuzz ARM data processing instructions", "[JitX64]") {
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}
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}
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TEST_CASE("Fuzz ARM load/store instructions (byte, half-word, word)", "[JitX64]") {
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const std::array<InstructionGenerator, 17> instructions = {{
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InstructionGenerator("cccc010pu0w1nnnnddddvvvvvvvvvvvv"), // LDR_imm
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InstructionGenerator("cccc011pu0w1nnnnddddvvvvvrr0mmmm"), // LDR_reg
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InstructionGenerator("cccc010pu1w1nnnnddddvvvvvvvvvvvv"), // LDRB_imm
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InstructionGenerator("cccc011pu1w1nnnnddddvvvvvrr0mmmm"), // LDRB_reg
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InstructionGenerator("cccc010pu0w0nnnnddddvvvvvvvvvvvv"), // STR_imm
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InstructionGenerator("cccc011pu0w0nnnnddddvvvvvrr0mmmm"), // STR_reg
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InstructionGenerator("cccc010pu1w0nnnnddddvvvvvvvvvvvv"), // STRB_imm
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InstructionGenerator("cccc011pu1w0nnnnddddvvvvvrr0mmmm"), // STRB_reg
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InstructionGenerator("cccc000pu1w1nnnnddddvvvv1011vvvv"), // LDRH_imm
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InstructionGenerator("cccc000pu0w1nnnndddd00001011mmmm"), // LDRH_reg
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InstructionGenerator("cccc000pu1w1nnnnddddvvvv1101vvvv"), // LDRSB_imm
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InstructionGenerator("cccc000pu0w1nnnndddd00001101mmmm"), // LDRSB_reg
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InstructionGenerator("cccc000pu1w1nnnnddddvvvv1111vvvv"), // LDRSH_imm
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InstructionGenerator("cccc000pu0w1nnnndddd00001111mmmm"), // LDRSH_reg
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InstructionGenerator("cccc000pu1w0nnnnddddvvvv1011vvvv"), // STRH_imm
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InstructionGenerator("cccc000pu0w0nnnndddd00001011mmmm"), // STRH_reg
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InstructionGenerator("1111000100000001000000e000000000"), // SETEND
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}};
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auto instruction_select = [&]() -> u32 {
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size_t inst_index = RandInt<size_t>(0, instructions.size() - 1);
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u32 cond = 0xE;
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// Have a one-in-twenty-five chance of actually having a cond.
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if (RandInt(1, 25) == 1) {
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cond = RandInt<u32>(0x0, 0xD);
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}
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u32 Rn = RandInt<u32>(0, 14);
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u32 Rd = RandInt<u32>(0, 14);
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u32 W = 0;
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u32 P = RandInt<u32>(0, 1);
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if (P) W = RandInt<u32>(0, 1);
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u32 U = RandInt<u32>(0, 1);
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u32 rand = RandInt<u32>(0, 0xFF);
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u32 Rm = RandInt<u32>(0, 14);
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if (W) {
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while (Rn == Rd) {
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Rn = RandInt<u32>(0, 14);
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Rd = RandInt<u32>(0, 14);
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}
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}
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u32 assemble_randoms = (Rm << 0) | (rand << 4) | (Rd << 12) | (Rn << 16) | (W << 21) | (U << 23) | (P << 24) | (cond << 28);
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return instructions[inst_index].Bits() | (assemble_randoms & (~instructions[inst_index].Mask()));
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};
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SECTION("short blocks") {
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FuzzJitArm(5, 6, 10000, instruction_select);
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}
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}
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TEST_CASE("Fuzz ARM load/store instructions (double-word)", "[JitX64]") {
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const std::array<InstructionGenerator, 4> instructions = {{
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InstructionGenerator("cccc000pu1w0nnnnddddvvvv1101vvvv"), // LDRD_imm
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InstructionGenerator("cccc000pu0w0nnnndddd00001101mmmm"), // LDRD_reg
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InstructionGenerator("cccc000pu1w0nnnnddddvvvv1111vvvv"), // STRD_imm
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InstructionGenerator("cccc000pu0w0nnnndddd00001111mmmm"), // STRD_reg
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}};
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auto instruction_select = [&]() -> u32 {
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size_t inst_index = RandInt<size_t>(0, instructions.size() - 1);
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u32 cond = 0xE;
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// Have a one-in-twenty-five chance of actually having a cond.
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if (RandInt(1, 25) == 1) {
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cond = RandInt<u32>(0x0, 0xD);
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}
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u32 Rn = RandInt<u32>(0, 6) * 2;
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u32 Rd = RandInt<u32>(0, 6) * 2;
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u32 W = 0;
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u32 P = RandInt<u32>(0, 1);
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if (P) W = RandInt<u32>(0, 1);
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u32 U = RandInt<u32>(0, 1);
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u32 rand = RandInt<u32>(0, 0xF);
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u32 Rm = RandInt<u32>(0, 14);
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if (W) {
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while (Rn == Rd) {
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Rn = RandInt<u32>(0, 6) * 2;
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Rd = RandInt<u32>(0, 6) * 2;
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}
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}
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while (Rm == Rd || Rm == Rd + 1) {
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Rm = RandInt<u32>(0, 14);
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}
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u32 assemble_randoms = (Rm << 0) | (rand << 4) | (Rd << 12) | (Rn << 16) | (W << 21) | (U << 23) | (P << 24) | (cond << 28);
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return instructions[inst_index].Bits() | (assemble_randoms & (~instructions[inst_index].Mask()));
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};
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SECTION("short blocks") {
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FuzzJitArm(5, 6, 10000, instruction_select);
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}
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}
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TEST_CASE("Fuzz ARM load/store multiple instructions", "[JitX64]") {
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const std::array<InstructionGenerator, 2> instructions = {{
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InstructionGenerator("cccc100pu0w1nnnnxxxxxxxxxxxxxxxx"), // LDM
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InstructionGenerator("cccc100pu0w0nnnnxxxxxxxxxxxxxxxx"), // STM
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}};
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auto instruction_select = [&]() -> u32 {
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size_t inst_index = RandInt<size_t>(0, instructions.size() - 1);
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u32 cond = 0xE;
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// Have a one-in-twenty-five chance of actually having a cond.
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if (RandInt(1, 25) == 1) {
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cond = RandInt<u32>(0x0, 0xD);
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}
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u32 reg_list = RandInt<u32>(1, 0xFFFF);
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u32 Rn = RandInt<u32>(0, 14);
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u32 flags = RandInt<u32>(0, 0xF);
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while (true) {
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if (inst_index == 1 && (flags & 2)) {
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if (reg_list & (1 << Rn))
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reg_list &= ~((1 << Rn) - 1);
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} else if (inst_index == 0 && (flags & 2)) {
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reg_list &= ~(1 << Rn);
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}
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if (reg_list)
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break;
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reg_list = RandInt<u32>(1, 0xFFFF);
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}
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u32 assemble_randoms = (reg_list << 0) | (Rn << 16) | (flags << 24) | (cond << 28);
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return instructions[inst_index].Bits() | (assemble_randoms & (~instructions[inst_index].Mask()));
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};
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FuzzJitArm(1, 1, 10000, instruction_select);
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}
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TEST_CASE("Fuzz ARM branch instructions", "[JitX64]") {
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const std::array<InstructionGenerator, 6> instructions = {{
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InstructionGenerator("1111101hvvvvvvvvvvvvvvvvvvvvvvvv"),
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@ -581,13 +719,11 @@ TEST_CASE("Fuzz ARM reversal instructions", "[JitX64]") {
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return Bits<0, 3>(instr) != 0b1111 && Bits<12, 15>(instr) != 0b1111;
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};
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const std::array<InstructionGenerator, 3> rev_instructions = {
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{
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const std::array<InstructionGenerator, 3> rev_instructions = {{
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InstructionGenerator("cccc011010111111dddd11110011mmmm", is_valid),
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InstructionGenerator("cccc011010111111dddd11111011mmmm", is_valid),
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InstructionGenerator("cccc011011111111dddd11111011mmmm", is_valid),
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}
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};
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}};
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SECTION("Reverse tests") {
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FuzzJitArm(1, 1, 10000, [&rev_instructions]() -> u32 {
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@ -596,133 +732,7 @@ TEST_CASE("Fuzz ARM reversal instructions", "[JitX64]") {
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}
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}
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/*
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TEST_CASE("Fuzz ARM Load/Store instructions", "[JitX64]") {
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auto forbid_r15 = [](u32 inst) -> bool {
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return Bits<12, 15>(inst) != 0b1111;
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};
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auto forbid_r14_and_r15 = [](u32 inst) -> bool {
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return Bits<13, 15>(inst) != 0b111;
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};
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const std::array<InstructionGenerator, 4> doubleword_instructions = {
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{
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// Load
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InstructionGenerator("0000000pu1w0nnnnddd0vvvv1101vvvv", forbid_r14_and_r15),
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InstructionGenerator("0000000pu0w0nnnnddd000001101mmmm", forbid_r14_and_r15),
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// Store
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InstructionGenerator("0000000pu1w0nnnnddd0vvvv1111vvvv", forbid_r14_and_r15),
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InstructionGenerator("0000000pu0w0nnnnddd000001111mmmm", forbid_r14_and_r15),
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}
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};
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const std::array<InstructionGenerator, 8> word_instructions = {
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{
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// Load
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InstructionGenerator("0000010pu0w1nnnnddddvvvvvvvvvvvv", forbid_r15),
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InstructionGenerator("0000011pu0w1nnnnddddvvvvvrr0mmmm", forbid_r15),
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InstructionGenerator("00000100u011nnnnttttmmmmmmmmmmmm", forbid_r15),
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InstructionGenerator("00000110u011nnnnttttvvvvvrr0mmmm", forbid_r15),
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// Store
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InstructionGenerator("0000010pu0w0nnnnddddvvvvvvvvvvvv", forbid_r15),
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InstructionGenerator("0000011pu0w0nnnnddddvvvvvrr0mmmm", forbid_r15),
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InstructionGenerator("00000100u010nnnnttttvvvvvvvvvvvv", forbid_r15),
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InstructionGenerator("00000110u010nnnnttttvvvvvrr0mmmm", forbid_r15),
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}
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};
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const std::array<InstructionGenerator, 6> halfword_instructions = {
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{
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// Load
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InstructionGenerator("0000000pu1w1nnnnddddvvvv1011vvvv", forbid_r15),
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InstructionGenerator("0000000pu0w1nnnndddd00001011mmmm", forbid_r15),
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// InstructionGenerator("----0000-111------------1011----"), // LDRHT (A1) Not available in ARMv6K
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// InstructionGenerator("----0000-011--------00001011----"), // LDRHT (A2) Not available in ARMv6K
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InstructionGenerator("0000000pu1w1nnnnddddvvvv1111vvvv", forbid_r15),
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InstructionGenerator("0000000pu0w1nnnndddd00001111mmmm", forbid_r15),
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// InstructionGenerator("----0000-111------------1111----"), // LDRSHT (A1) Not available in ARMv6K
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// InstructionGenerator("----0000-011--------00001111----"), // LDRSHT (A2) Not available in ARMv6K
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// Store
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InstructionGenerator("0000000pu1w0nnnnddddvvvv1011vvvv", forbid_r15),
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InstructionGenerator("0000000pu0w0nnnndddd00001011mmmm", forbid_r15),
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// InstructionGenerator("----0000-110------------1011----"), // STRHT (A1) Not available in ARMv6K
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// InstructionGenerator("----0000-010--------00001011----"), // STRHT (A2) Not available in ARMv6K
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}
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};
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const std::array<InstructionGenerator, 10> byte_instructions = {
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{
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// Load
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InstructionGenerator("0000010pu1w1nnnnddddvvvvvvvvvvvv", forbid_r15),
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InstructionGenerator("0000011pu1w1nnnnddddvvvvvrr0mmmm", forbid_r15),
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InstructionGenerator("00000100u111nnnnttttvvvvvvvvvvvv", forbid_r15),
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InstructionGenerator("00000110u111nnnnttttvvvvvrr0mmmm", forbid_r15),
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InstructionGenerator("0000000pu1w1nnnnddddvvvv1101vvvv", forbid_r15),
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InstructionGenerator("0000000pu0w1nnnndddd00001101mmmm", forbid_r15),
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// InstructionGenerator("----0000-111------------1101----"), // LDRSBT (A1) Not available in ARMv6K
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// InstructionGenerator("----0000-011--------00001101----"), // LDRSBT (A2) Not available in ARMv6K
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// Store
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InstructionGenerator("0000010pu1w0nnnnddddvvvvvvvvvvvv", forbid_r15),
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InstructionGenerator("0000011pu1w0nnnnddddvvvvvrr0mmmm", forbid_r15),
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InstructionGenerator("00000100u110nnnnttttvvvvvvvvvvvv", forbid_r15),
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InstructionGenerator("00000110u110nnnnttttvvvvvrr0mmmm", forbid_r15),
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}
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};
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SECTION("Doubleword tests") {
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FuzzJitArm(1, 1, 10000, [&doubleword_instructions]() -> u32 {
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return doubleword_instructions[RandInt<size_t>(0, doubleword_instructions.size() - 1)].Generate();
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});
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}
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SECTION("Word tests") {
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FuzzJitArm(1, 1, 10000, [&word_instructions]() -> u32 {
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return word_instructions[RandInt<size_t>(0, word_instructions.size() - 1)].Generate();
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});
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}
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SECTION("Halfword tests") {
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FuzzJitArm(1, 1, 10000, [&halfword_instructions]() -> u32 {
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return halfword_instructions[RandInt<size_t>(0, halfword_instructions.size() - 1)].Generate();
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});
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}
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SECTION("Byte tests") {
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FuzzJitArm(1, 1, 10000, [&byte_instructions]() -> u32 {
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return byte_instructions[RandInt<size_t>(0, byte_instructions.size() - 1)].Generate();
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});
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}
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SECTION("Mixed tests") {
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FuzzJitArm(10, 10, 10000, [&]() -> u32 {
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switch (RandInt(0, 3)) {
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case 0:
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return doubleword_instructions[RandInt<size_t>(0, doubleword_instructions.size() - 1)].Generate();
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case 1:
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return word_instructions[RandInt<size_t>(0, word_instructions.size() - 1)].Generate();
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case 2:
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return halfword_instructions[RandInt<size_t>(0, halfword_instructions.size() - 1)].Generate();
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case 3:
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return byte_instructions[RandInt<size_t>(0, byte_instructions.size() - 1)].Generate();
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}
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return 0;
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});
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}
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SECTION("Write to PC") {
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// TODO
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FAIL();
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}
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}
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*/
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TEST_CASE("Fuzz ARM extension instructions", "[JitX64]") {
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const auto is_valid = [](u32 instr) -> bool {
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@ -730,27 +740,23 @@ TEST_CASE("Fuzz ARM extension instructions", "[JitX64]") {
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return Bits<0, 3>(instr) != 0b1111 && Bits<12, 15>(instr) != 0b1111;
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};
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const std::array<InstructionGenerator, 6> signed_instructions = {
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{
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const std::array<InstructionGenerator, 6> signed_instructions = {{
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InstructionGenerator("cccc011010101111ddddrr000111mmmm", is_valid),
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InstructionGenerator("cccc011010001111ddddrr000111mmmm", is_valid),
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InstructionGenerator("cccc011010111111ddddrr000111mmmm", is_valid),
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InstructionGenerator("cccc01101010nnnnddddrr000111mmmm", is_valid),
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InstructionGenerator("cccc01101000nnnnddddrr000111mmmm", is_valid),
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InstructionGenerator("cccc01101011nnnnddddrr000111mmmm", is_valid),
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}
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};
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}};
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const std::array<InstructionGenerator, 6> unsigned_instructions = {
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{
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const std::array<InstructionGenerator, 6> unsigned_instructions = {{
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InstructionGenerator("cccc011011101111ddddrr000111mmmm", is_valid),
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InstructionGenerator("cccc011011001111ddddrr000111mmmm", is_valid),
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InstructionGenerator("cccc011011111111ddddrr000111mmmm", is_valid),
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InstructionGenerator("cccc01101110nnnnddddrr000111mmmm", is_valid),
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InstructionGenerator("cccc01101100nnnnddddrr000111mmmm", is_valid),
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||||
InstructionGenerator("cccc01101111nnnnddddrr000111mmmm", is_valid),
|
||||
}
|
||||
};
|
||||
}};
|
||||
|
||||
SECTION("Signed extension") {
|
||||
FuzzJitArm(1, 1, 10000, [&signed_instructions]() -> u32 {
|
||||
|
|
@ -780,8 +786,7 @@ TEST_CASE("Fuzz ARM multiply instructions", "[JitX64]") {
|
|||
Bits<12, 15>(inst) != Bits<16, 19>(inst);
|
||||
};
|
||||
|
||||
const std::array<InstructionGenerator, 10> instructions = {
|
||||
{
|
||||
const std::array<InstructionGenerator, 10> instructions = {{
|
||||
InstructionGenerator("cccc0000001Sddddaaaammmm1001nnnn", validate_d_a_m_n), // MLA
|
||||
InstructionGenerator("cccc0000000Sdddd0000mmmm1001nnnn", validate_d_m_n), // MUL
|
||||
|
||||
|
|
@ -808,8 +813,7 @@ TEST_CASE("Fuzz ARM multiply instructions", "[JitX64]") {
|
|||
//InstructionGenerator("cccc01110100ddddaaaammmm01M1nnnn", validate_d_a_m_n), // SMLSLD
|
||||
//InstructionGenerator("cccc01110000dddd1111mmmm00M1nnnn", validate_d_m_n), // SMUAD
|
||||
//InstructionGenerator("cccc01110000dddd1111mmmm01M1nnnn", validate_d_m_n), // SMUSD
|
||||
}
|
||||
};
|
||||
}};
|
||||
|
||||
SECTION("Multiply") {
|
||||
FuzzJitArm(2, 2, 10000, [&]() -> u32 {
|
||||
|
|
|
|||
Loading…
Reference in a new issue