From b178ab3becc77b02d22c68f673465d0d7227bba1 Mon Sep 17 00:00:00 2001
From: MerryMage <MerryMage@users.noreply.github.com>
Date: Thu, 15 Dec 2016 21:32:20 +0000
Subject: [PATCH] Replace (void)(...); idiom with UNUSED macro

---
 src/common/common_types.h                     |  2 +
 .../translate_arm/exception_generating.cpp    |  2 +-
 .../translate/translate_arm/extension.cpp     |  6 +--
 .../translate/translate_arm/parallel.cpp      | 40 +++++++++----------
 .../translate/translate_arm/translate_arm.h   | 20 +++++-----
 5 files changed, 36 insertions(+), 34 deletions(-)

diff --git a/src/common/common_types.h b/src/common/common_types.h
index 005541f9..06897167 100644
--- a/src/common/common_types.h
+++ b/src/common/common_types.h
@@ -27,3 +27,5 @@ using f32 = float;
 using f64 = double;
 static_assert(sizeof(f32) == sizeof(u32), "f32 must be 32 bits wide");
 static_assert(sizeof(f64) == sizeof(u64), "f64 must be 64 bits wide");
+
+#define UNUSED(...) (void)([__VA_ARGS__](){})
diff --git a/src/frontend/translate/translate_arm/exception_generating.cpp b/src/frontend/translate/translate_arm/exception_generating.cpp
index 8e1d3275..a808b00c 100644
--- a/src/frontend/translate/translate_arm/exception_generating.cpp
+++ b/src/frontend/translate/translate_arm/exception_generating.cpp
@@ -10,7 +10,7 @@ namespace Dynarmic {
 namespace Arm {
 
 bool ArmTranslatorVisitor::arm_BKPT(Cond cond, Imm12 imm12, Imm4 imm4) {
-    (void)(cond, imm12, imm4); // Unused
+    UNUSED(cond, imm12, imm4);
     return InterpretThisInstruction();
 }
 
diff --git a/src/frontend/translate/translate_arm/extension.cpp b/src/frontend/translate/translate_arm/extension.cpp
index 1635075e..1df77459 100644
--- a/src/frontend/translate/translate_arm/extension.cpp
+++ b/src/frontend/translate/translate_arm/extension.cpp
@@ -40,7 +40,7 @@ bool ArmTranslatorVisitor::arm_SXTAB(Cond cond, Reg n, Reg d, SignExtendRotation
 }
 
 bool ArmTranslatorVisitor::arm_SXTAB16(Cond cond, Reg n, Reg d, SignExtendRotation rotate, Reg m) {
-    (void)(cond, n, d, rotate, m); // Unused
+    UNUSED(cond, n, d, rotate, m);
     return InterpretThisInstruction();
 }
 
@@ -68,7 +68,7 @@ bool ArmTranslatorVisitor::arm_SXTB(Cond cond, Reg d, SignExtendRotation rotate,
 }
 
 bool ArmTranslatorVisitor::arm_SXTB16(Cond cond, Reg d, SignExtendRotation rotate, Reg m) {
-    (void)(cond, d, rotate, m); // Unused
+    UNUSED(cond, d, rotate, m);
     return InterpretThisInstruction();
 }
 
@@ -96,7 +96,7 @@ bool ArmTranslatorVisitor::arm_UXTAB(Cond cond, Reg n, Reg d, SignExtendRotation
 }
 
 bool ArmTranslatorVisitor::arm_UXTAB16(Cond cond, Reg n, Reg d, SignExtendRotation rotate, Reg m) {
-    (void)(cond, n, d, rotate, m); // Unused
+    UNUSED(cond, n, d, rotate, m);
     return InterpretThisInstruction();
 }
 
diff --git a/src/frontend/translate/translate_arm/parallel.cpp b/src/frontend/translate/translate_arm/parallel.cpp
index 394eedd4..5f374a30 100644
--- a/src/frontend/translate/translate_arm/parallel.cpp
+++ b/src/frontend/translate/translate_arm/parallel.cpp
@@ -11,32 +11,32 @@ namespace Arm {
 
 // Parallel Add/Subtract (Modulo arithmetic) instructions
 bool ArmTranslatorVisitor::arm_SADD8(Cond cond, Reg n, Reg d, Reg m) {
-    (void)(cond, n, d, m); // Unused
+    UNUSED(cond, n, d, m);
     return InterpretThisInstruction();
 }
 
 bool ArmTranslatorVisitor::arm_SADD16(Cond cond, Reg n, Reg d, Reg m) {
-    (void)(cond, n, d, m); // Unused
+    UNUSED(cond, n, d, m);
     return InterpretThisInstruction();
 }
 
 bool ArmTranslatorVisitor::arm_SASX(Cond cond, Reg n, Reg d, Reg m) {
-    (void)(cond, n, d, m); // Unused
+    UNUSED(cond, n, d, m);
     return InterpretThisInstruction();
 }
 
 bool ArmTranslatorVisitor::arm_SSAX(Cond cond, Reg n, Reg d, Reg m) {
-    (void)(cond, n, d, m); // Unused
+    UNUSED(cond, n, d, m);
     return InterpretThisInstruction();
 }
 
 bool ArmTranslatorVisitor::arm_SSUB8(Cond cond, Reg n, Reg d, Reg m) {
-    (void)(cond, n, d, m); // Unused
+    UNUSED(cond, n, d, m);
     return InterpretThisInstruction();
 }
 
 bool ArmTranslatorVisitor::arm_SSUB16(Cond cond, Reg n, Reg d, Reg m) {
-    (void)(cond, n, d, m); // Unused
+    UNUSED(cond, n, d, m);
     return InterpretThisInstruction();
 }
 
@@ -52,17 +52,17 @@ bool ArmTranslatorVisitor::arm_UADD8(Cond cond, Reg n, Reg d, Reg m) {
 }
 
 bool ArmTranslatorVisitor::arm_UADD16(Cond cond, Reg n, Reg d, Reg m) {
-    (void)(cond, n, d, m); // Unused
+    UNUSED(cond, n, d, m);
     return InterpretThisInstruction();
 }
 
 bool ArmTranslatorVisitor::arm_UASX(Cond cond, Reg n, Reg d, Reg m) {
-    (void)(cond, n, d, m); // Unused
+    UNUSED(cond, n, d, m);
     return InterpretThisInstruction();
 }
 
 bool ArmTranslatorVisitor::arm_USAX(Cond cond, Reg n, Reg d, Reg m) {
-    (void)(cond, n, d, m); // Unused
+    UNUSED(cond, n, d, m);
     return InterpretThisInstruction();
 }
 
@@ -78,7 +78,7 @@ bool ArmTranslatorVisitor::arm_USUB8(Cond cond, Reg n, Reg d, Reg m) {
 }
 
 bool ArmTranslatorVisitor::arm_USUB16(Cond cond, Reg n, Reg d, Reg m) {
-    (void)(cond, n, d, m); // Unused
+    UNUSED(cond, n, d, m);
     return InterpretThisInstruction();
 }
 
@@ -105,12 +105,12 @@ bool ArmTranslatorVisitor::arm_QADD16(Cond cond, Reg n, Reg d, Reg m) {
 }
 
 bool ArmTranslatorVisitor::arm_QASX(Cond cond, Reg n, Reg d, Reg m) {
-    (void)(cond, n, d, m); // Unused
+    UNUSED(cond, n, d, m);
     return InterpretThisInstruction();
 }
 
 bool ArmTranslatorVisitor::arm_QSAX(Cond cond, Reg n, Reg d, Reg m) {
-    (void)(cond, n, d, m); // Unused
+    UNUSED(cond, n, d, m);
     return InterpretThisInstruction();
 }
 
@@ -151,12 +151,12 @@ bool ArmTranslatorVisitor::arm_UQADD16(Cond cond, Reg n, Reg d, Reg m) {
 }
 
 bool ArmTranslatorVisitor::arm_UQASX(Cond cond, Reg n, Reg d, Reg m) {
-    (void)(cond, n, d, m); // Unused
+    UNUSED(cond, n, d, m);
     return InterpretThisInstruction();
 }
 
 bool ArmTranslatorVisitor::arm_UQSAX(Cond cond, Reg n, Reg d, Reg m) {
-    (void)(cond, n, d, m); // Unused
+    UNUSED(cond, n, d, m);
     return InterpretThisInstruction();
 }
 
@@ -203,22 +203,22 @@ bool ArmTranslatorVisitor::arm_SHADD16(Cond cond, Reg n, Reg d, Reg m) {
 }
 
 bool ArmTranslatorVisitor::arm_SHASX(Cond cond, Reg n, Reg d, Reg m) {
-    (void)(cond, n, d, m); // Unused
+    UNUSED(cond, n, d, m);
     return InterpretThisInstruction();
 }
 
 bool ArmTranslatorVisitor::arm_SHSAX(Cond cond, Reg n, Reg d, Reg m) {
-    (void)(cond, n, d, m); // Unused
+    UNUSED(cond, n, d, m);
     return InterpretThisInstruction();
 }
 
 bool ArmTranslatorVisitor::arm_SHSUB8(Cond cond, Reg n, Reg d, Reg m) {
-    (void)(cond, n, d, m); // Unused
+    UNUSED(cond, n, d, m);
     return InterpretThisInstruction();
 }
 
 bool ArmTranslatorVisitor::arm_SHSUB16(Cond cond, Reg n, Reg d, Reg m) {
-    (void)(cond, n, d, m); // Unused
+    UNUSED(cond, n, d, m);
     return InterpretThisInstruction();
 }
 
@@ -243,12 +243,12 @@ bool ArmTranslatorVisitor::arm_UHADD16(Cond cond, Reg n, Reg d, Reg m) {
 }
 
 bool ArmTranslatorVisitor::arm_UHASX(Cond cond, Reg n, Reg d, Reg m) {
-    (void)(cond, n, d, m); // Unused
+    UNUSED(cond, n, d, m);
     return InterpretThisInstruction();
 }
 
 bool ArmTranslatorVisitor::arm_UHSAX(Cond cond, Reg n, Reg d, Reg m) {
-    (void)(cond, n, d, m); // Unused
+    UNUSED(cond, n, d, m);
     return InterpretThisInstruction();
 }
 
diff --git a/src/frontend/translate/translate_arm/translate_arm.h b/src/frontend/translate/translate_arm/translate_arm.h
index 6413d8f2..0ede9df4 100644
--- a/src/frontend/translate/translate_arm/translate_arm.h
+++ b/src/frontend/translate/translate_arm/translate_arm.h
@@ -215,11 +215,11 @@ struct ArmTranslatorVisitor final {
 
     // Unsigned sum of absolute difference functions
     bool arm_USAD8(Cond cond, Reg d, Reg m, Reg n) {
-        (void)(cond, d, m, n); // Unused
+        UNUSED(cond, d, m, n);
         return InterpretThisInstruction();
     }
     bool arm_USADA8(Cond cond, Reg d, Reg a, Reg m, Reg n) {
-        (void)(cond, d, a, m, n); // Unused
+        UNUSED(cond, d, a, m, n);
         return InterpretThisInstruction();
     }
 
@@ -234,19 +234,19 @@ struct ArmTranslatorVisitor final {
 
     // Saturation instructions
     bool arm_SSAT(Cond cond, Imm5 sat_imm, Reg d, Imm5 imm5, bool sh, Reg n) {
-        (void)(cond, sat_imm, d, imm5, sh, n); // Unused
+        UNUSED(cond, sat_imm, d, imm5, sh, n);
         return InterpretThisInstruction();
     }
     bool arm_SSAT16(Cond cond, Imm4 sat_imm, Reg d, Reg n) {
-        (void)(cond, sat_imm, d, n); // Unused
+        UNUSED(cond, sat_imm, d, n);
         return InterpretThisInstruction();
     }
     bool arm_USAT(Cond cond, Imm5 sat_imm, Reg d, Imm5 imm5, bool sh, Reg n) {
-        (void)(cond, sat_imm, d, imm5, sh, n); // Unused
+        UNUSED(cond, sat_imm, d, imm5, sh, n);
         return InterpretThisInstruction();
     }
     bool arm_USAT16(Cond cond, Imm4 sat_imm, Reg d, Reg n) {
-        (void)(cond, sat_imm, d, n); // Unused
+        UNUSED(cond, sat_imm, d, n);
         return InterpretThisInstruction();
     }
 
@@ -327,19 +327,19 @@ struct ArmTranslatorVisitor final {
 
     // Saturated Add/Subtract instructions
     bool arm_QADD(Cond cond, Reg n, Reg d, Reg m) {
-        (void)(cond, d, m, n); // Unused
+        UNUSED(cond, d, m, n);
         return InterpretThisInstruction();
     }
     bool arm_QSUB(Cond cond, Reg n, Reg d, Reg m) {
-        (void)(cond, d, m, n); // Unused
+        UNUSED(cond, d, m, n);
         return InterpretThisInstruction();
     }
     bool arm_QDADD(Cond cond, Reg n, Reg d, Reg m) {
-        (void)(cond, d, m, n); // Unused
+        UNUSED(cond, d, m, n);
         return InterpretThisInstruction();
     }
     bool arm_QDSUB(Cond cond, Reg n, Reg d, Reg m) {
-        (void)(cond, d, m, n); // Unused
+        UNUSED(cond, d, m, n);
         return InterpretThisInstruction();
     }