thumb32: Implement ASR (register)
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3 changed files with 15 additions and 1 deletions
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@ -191,7 +191,7 @@ INST(thumb32_BLX_imm, "BLX (imm)", "11110Svvvvvvvvvv11j0jv
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// Data Processing (register)
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INST(thumb32_LSL_reg, "LSL (reg)", "111110100000mmmm1111dddd0000ssss")
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INST(thumb32_LSR_reg, "LSR (reg)", "111110100010mmmm1111dddd0000ssss")
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//INST(thumb32_ASR_reg, "ASR (reg)", "11111010010-----1111----0000----")
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INST(thumb32_ASR_reg, "ASR (reg)", "111110100100mmmm1111dddd0000ssss")
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//INST(thumb32_ROR_reg, "ROR (reg)", "11111010011-----1111----0000----")
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INST(thumb32_SXTH, "SXTH", "11111010000011111111dddd10rrmmmm")
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INST(thumb32_SXTAH, "SXTAH", "111110100000nnnn1111dddd10rrmmmm")
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@ -11,6 +11,19 @@ static IR::U32 Rotate(A32::IREmitter& ir, Reg m, SignExtendRotation rotate) {
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return ir.RotateRight(ir.GetRegister(m), ir.Imm8(rotate_by), ir.Imm1(0)).result;
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}
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bool ThumbTranslatorVisitor::thumb32_ASR_reg(Reg m, Reg d, Reg s) {
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if (d == Reg::PC || m == Reg::PC || s == Reg::PC) {
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return UnpredictableInstruction();
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}
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const auto shift_s = ir.LeastSignificantByte(ir.GetRegister(s));
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const auto apsr_c = ir.GetCFlag();
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const auto result_carry = ir.ArithmeticShiftRight(ir.GetRegister(m), shift_s, apsr_c);
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ir.SetRegister(d, result_carry.result);
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return true;
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}
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bool ThumbTranslatorVisitor::thumb32_LSL_reg(Reg m, Reg d, Reg s) {
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if (d == Reg::PC || m == Reg::PC || s == Reg::PC) {
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return UnpredictableInstruction();
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@ -182,6 +182,7 @@ struct ThumbTranslatorVisitor final {
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bool thumb32_BLX_imm(Imm<1> S, Imm<10> hi, Imm<1> j1, Imm<1> j2, Imm<11> lo);
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// thumb32 data processing (register) instructions
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bool thumb32_ASR_reg(Reg m, Reg d, Reg s);
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bool thumb32_LSL_reg(Reg m, Reg d, Reg s);
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bool thumb32_LSR_reg(Reg m, Reg d, Reg s);
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bool thumb32_SXTB(Reg d, SignExtendRotation rotate, Reg m);
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