diff --git a/src/backend_x64/emit_x64.cpp b/src/backend_x64/emit_x64.cpp
index ae1db333..d818d593 100644
--- a/src/backend_x64/emit_x64.cpp
+++ b/src/backend_x64/emit_x64.cpp
@@ -451,6 +451,7 @@ void EmitX64::EmitSubWithCarry(IR::Value* value_) {
                       : X64Reg::INVALID_REG;
 
     // TODO: Consider using LEA.
+    // TODO: Optimize case when result isn't used but flags are (use a CMP instruction instead).
     // Note that x64 CF is inverse of what the ARM carry flag is here.
 
     code->BT(32, R(carry), Imm8(0));
diff --git a/src/frontend/decoder/thumb1.h b/src/frontend/decoder/thumb1.h
index 89f18f0e..40858a5d 100644
--- a/src/frontend/decoder/thumb1.h
+++ b/src/frontend/decoder/thumb1.h
@@ -56,7 +56,7 @@ private:
 };
 
 template <typename V>
-static const std::array<Thumb1Matcher<V>, 15> g_thumb1_instruction_table {{
+static const std::array<Thumb1Matcher<V>, 16> g_thumb1_instruction_table {{
 
 #define INST(fn, name, bitstring) detail::detail<Thumb1Matcher, u16, 16>::GetMatcher<decltype(fn), fn>(name, bitstring)
 
@@ -69,7 +69,7 @@ static const std::array<Thumb1Matcher<V>, 15> g_thumb1_instruction_table {{
     { INST(&V::thumb1_ADD_imm,        "ADD (imm)",                "0001110vvvnnnddd") },
     { INST(&V::thumb1_SUB_imm,        "SUB (imm)",                "0001111vvvnnnddd") },
     { INST(&V::thumb1_MOV_imm,        "MOV (imm)",                "00100dddvvvvvvvv") },
-    //{ INST(&V::thumb1_CMP_ri,         "CMP (ri)",                 "00101dddvvvvvvvv") },
+    { INST(&V::thumb1_CMP_imm,        "CMP (imm)",                "00101nnnvvvvvvvv") },
     //{ INST(&V::thumb1_ADD_ri,         "ADD (ri)",                 "00110dddvvvvvvvv") },
     //{ INST(&V::thumb1_SUB_ri,         "SUB (ri)",                 "00111dddvvvvvvvv") },
 
diff --git a/src/frontend/disassembler_thumb.cpp b/src/frontend/disassembler_thumb.cpp
index d0d95eaf..084a643e 100644
--- a/src/frontend/disassembler_thumb.cpp
+++ b/src/frontend/disassembler_thumb.cpp
@@ -134,6 +134,10 @@ public:
         return Common::StringFromFormat("movs %s, #%u", RegStr(d), imm8);
     }
 
+    std::string thumb1_CMP_imm(Reg n, Imm8 imm8) {
+        return Common::StringFromFormat("cmp %s, #%u", RegStr(n), imm8);
+    }
+
     std::string thumb1_AND_reg(Reg m, Reg d_n) {
         return Common::StringFromFormat("ands %s, %s", RegStr(d_n), RegStr(m));
     }
diff --git a/src/frontend/translate_thumb.cpp b/src/frontend/translate_thumb.cpp
index a97d4dea..631010a0 100644
--- a/src/frontend/translate_thumb.cpp
+++ b/src/frontend/translate_thumb.cpp
@@ -120,6 +120,16 @@ struct TranslatorVisitor final {
         ir.SetZFlag(ir.IsZero(result));
         return true;
     }
+    bool thumb1_CMP_imm(Reg n, Imm8 imm8) {
+        u32 imm32 = imm8 & 0xFF;
+        // CMP <Rn>, #<imm8>
+        auto result = ir.SubWithCarry(ir.GetRegister(n), ir.Imm32(imm32), ir.Imm1(1));
+        ir.SetNFlag(ir.MostSignificantBit(result.result));
+        ir.SetZFlag(ir.IsZero(result.result));
+        ir.SetCFlag(result.carry);
+        ir.SetVFlag(result.overflow);
+        return true;
+    }
 
     bool thumb1_AND_reg(Reg m, Reg d_n) {
         const Reg d = d_n, n = d_n;