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A64: Implement NOT (vector)

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Lioncash 2018-02-11 14:16:47 -05:00 committed by MerryMage
parent 2cb0a699ba
commit a9153218bd
2 changed files with 15 additions and 1 deletions
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2
src/frontend/A64/decoder/a64.inc
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@ -644,7 +644,7 @@ INST(XTN, "XTN, XTN2", "0Q001
//INST(CLZ_asimd, "CLZ (vector)", "0Q101110zz100000010010nnnnnddddd") //INST(CLZ_asimd, "CLZ (vector)", "0Q101110zz100000010010nnnnnddddd")
//INST(UADALP, "UADALP", "0Q101110zz100000011010nnnnnddddd") //INST(UADALP, "UADALP", "0Q101110zz100000011010nnnnnddddd")
//INST(SHLL, "SHLL, SHLL2", "0Q101110zz100001001110nnnnnddddd") //INST(SHLL, "SHLL, SHLL2", "0Q101110zz100001001110nnnnnddddd")
//INST(NOT, "NOT", "0Q10111000100000010110nnnnnddddd") INST(NOT, "NOT", "0Q10111000100000010110nnnnnddddd")
//INST(RBIT_asimd, "RBIT (vector)", "0Q10111001100000010110nnnnnddddd") //INST(RBIT_asimd, "RBIT (vector)", "0Q10111001100000010110nnnnnddddd")
//INST(URSQRTE, "URSQRTE", "0Q1011101z100001110010nnnnnddddd") //INST(URSQRTE, "URSQRTE", "0Q1011101z100001110010nnnnnddddd")

14
src/frontend/A64/translate/impl/simd_two_register_misc.cpp
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@ -36,4 +36,18 @@ bool TranslatorVisitor::XTN(bool Q, Imm<2> size, Vec Vn, Vec Vd) {
return true; return true;
} }
bool TranslatorVisitor::NOT(bool Q, Vec Vn, Vec Vd) {
const size_t datasize = Q ? 128 : 64;
const IR::U128 operand = V(datasize, Vn);
IR::U128 result = ir.VectorNot(operand);
if (datasize == 64) {
result = ir.VectorZeroUpper(result);
}
V(datasize, Vd, result);
return true;
}
} // namespace Dynarmic::A64 } // namespace Dynarmic::A64