From a72813599a11b4319b29a179527f1311a10fdff7 Mon Sep 17 00:00:00 2001
From: Lioncash <mathew1800@gmail.com>
Date: Fri, 1 Mar 2019 01:51:47 -0500
Subject: [PATCH] translate_arm/reversal: Invert conditionals where applicable

---
 .../A32/translate/translate_arm/reversal.cpp  | 51 +++++++++++--------
 1 file changed, 31 insertions(+), 20 deletions(-)

diff --git a/src/frontend/A32/translate/translate_arm/reversal.cpp b/src/frontend/A32/translate/translate_arm/reversal.cpp
index f561bdd9..ae7f4506 100644
--- a/src/frontend/A32/translate/translate_arm/reversal.cpp
+++ b/src/frontend/A32/translate/translate_arm/reversal.cpp
@@ -8,41 +8,52 @@
 
 namespace Dynarmic::A32 {
 
+// REV<c> <Rd>, <Rm>
 bool ArmTranslatorVisitor::arm_REV(Cond cond, Reg d, Reg m) {
-    // REV<c> <Rd>, <Rm>
-    if (d == Reg::PC || m == Reg::PC)
+    if (d == Reg::PC || m == Reg::PC) {
         return UnpredictableInstruction();
-
-    if (ConditionPassed(cond)) {
-        auto result = ir.ByteReverseWord(ir.GetRegister(m));
-        ir.SetRegister(d, result);
     }
+
+    if (!ConditionPassed(cond)) {
+        return true;
+    }
+
+    const auto result = ir.ByteReverseWord(ir.GetRegister(m));
+    ir.SetRegister(d, result);
     return true;
 }
 
+// REV16<c> <Rd>, <Rm>
 bool ArmTranslatorVisitor::arm_REV16(Cond cond, Reg d, Reg m) {
-    if (d == Reg::PC || m == Reg::PC)
+    if (d == Reg::PC || m == Reg::PC) {
         return UnpredictableInstruction();
-
-    if (ConditionPassed(cond)) {
-        auto reg_m = ir.GetRegister(m);
-        auto lo = ir.And(ir.LogicalShiftRight(reg_m, ir.Imm8(8), ir.Imm1(0)).result, ir.Imm32(0x00FF00FF));
-        auto hi = ir.And(ir.LogicalShiftLeft(reg_m, ir.Imm8(8), ir.Imm1(0)).result, ir.Imm32(0xFF00FF00));
-        auto result = ir.Or(lo, hi);
-        ir.SetRegister(d, result);
     }
+
+    if (!ConditionPassed(cond)) {
+        return true;
+    }
+
+    const auto reg_m = ir.GetRegister(m);
+    const auto lo = ir.And(ir.LogicalShiftRight(reg_m, ir.Imm8(8), ir.Imm1(0)).result, ir.Imm32(0x00FF00FF));
+    const auto hi = ir.And(ir.LogicalShiftLeft(reg_m, ir.Imm8(8), ir.Imm1(0)).result, ir.Imm32(0xFF00FF00));
+    const auto result = ir.Or(lo, hi);
+
+    ir.SetRegister(d, result);
     return true;
 }
 
+// REVSH<c> <Rd>, <Rm>
 bool ArmTranslatorVisitor::arm_REVSH(Cond cond, Reg d, Reg m) {
-    // REVSH<c> <Rd>, <Rm>
-    if (d == Reg::PC || m == Reg::PC)
+    if (d == Reg::PC || m == Reg::PC) {
         return UnpredictableInstruction();
-
-    if (ConditionPassed(cond)) {
-        auto rev_half = ir.ByteReverseHalf(ir.LeastSignificantHalf(ir.GetRegister(m)));
-        ir.SetRegister(d, ir.SignExtendHalfToWord(rev_half));
     }
+
+    if (!ConditionPassed(cond)) {
+        return true;
+    }
+
+    const auto rev_half = ir.ByteReverseHalf(ir.LeastSignificantHalf(ir.GetRegister(m)));
+    ir.SetRegister(d, ir.SignExtendHalfToWord(rev_half));
     return true;
 }