suyu/dynarmic
28
1
Fork 1
Code Issues Pull requests Projects Releases Packages Wiki Activity

Implement thumb1_ADD_imm

Browse source
This commit is contained in:
MerryMage 2016-07-08 19:15:30 +08:00
parent 92142d5a22
commit a2e40eb922
4 changed files with 19 additions and 2 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

1
src/frontend/arm_types.h
View file

@ -36,6 +36,7 @@ inline Reg operator+(Reg reg, int number) {
return static_cast<Reg>(new_reg); return static_cast<Reg>(new_reg);
} }
using Imm3 = u32;
using Imm4 = u32; using Imm4 = u32;
using Imm5 = u32; using Imm5 = u32;
using Imm8 = u32; using Imm8 = u32;

4
src/frontend/decoder/thumb1.h
View file

@ -56,7 +56,7 @@ private:
}; };
template <typename V> template <typename V>
static const std::array<Thumb1Matcher<V>, 12> g_thumb1_instruction_table {{ static const std::array<Thumb1Matcher<V>, 13> g_thumb1_instruction_table {{
#define INST(fn, name, bitstring) detail::detail<Thumb1Matcher, u16, 16>::GetMatcher<decltype(fn), fn>(name, bitstring) #define INST(fn, name, bitstring) detail::detail<Thumb1Matcher, u16, 16>::GetMatcher<decltype(fn), fn>(name, bitstring)
@ -66,7 +66,7 @@ static const std::array<Thumb1Matcher<V>, 12> g_thumb1_instruction_table {{
{ INST(&V::thumb1_ASR_imm, "ASR (imm)", "00010vvvvvmmmddd") }, { INST(&V::thumb1_ASR_imm, "ASR (imm)", "00010vvvvvmmmddd") },
{ INST(&V::thumb1_ADD_reg_t1, "ADD (reg, T1)", "0001100mmmnnnddd") }, { INST(&V::thumb1_ADD_reg_t1, "ADD (reg, T1)", "0001100mmmnnnddd") },
{ INST(&V::thumb1_SUB_reg, "SUB (reg)", "0001101mmmnnnddd") }, { INST(&V::thumb1_SUB_reg, "SUB (reg)", "0001101mmmnnnddd") },
//{ INST(&V::thumb1_ADD_rri, "ADD (rri)", "0001110mmmnnnddd") }, { INST(&V::thumb1_ADD_imm, "ADD (imm)", "0001110vvvnnnddd") },
//{ INST(&V::thumb1_SUB_rri, "SUB (rri)", "0001111mmmnnnddd") }, //{ INST(&V::thumb1_SUB_rri, "SUB (rri)", "0001111mmmnnnddd") },
//{ INST(&V::thumb1_MOV_ri, "MOV (ri)", "00100dddvvvvvvvv") }, //{ INST(&V::thumb1_MOV_ri, "MOV (ri)", "00100dddvvvvvvvv") },
//{ INST(&V::thumb1_CMP_ri, "CMP (ri)", "00101dddvvvvvvvv") }, //{ INST(&V::thumb1_CMP_ri, "CMP (ri)", "00101dddvvvvvvvv") },

4
src/frontend/disassembler_thumb.cpp
View file

@ -122,6 +122,10 @@ public:
return Common::StringFromFormat("subs %s, %s, %s", RegStr(d), RegStr(n), RegStr(m)); return Common::StringFromFormat("subs %s, %s, %s", RegStr(d), RegStr(n), RegStr(m));
} }
std::string thumb1_ADD_imm(Imm3 imm3, Reg n, Reg d) {
return Common::StringFromFormat("adds %s, %s, #%u", RegStr(d), RegStr(n), imm3);
}
std::string thumb1_AND_reg(Reg m, Reg d_n) { std::string thumb1_AND_reg(Reg m, Reg d_n) {
return Common::StringFromFormat("ands %s, %s", RegStr(d_n), RegStr(m)); return Common::StringFromFormat("ands %s, %s", RegStr(d_n), RegStr(m));
} }

12
src/frontend/translate_thumb.cpp
View file

@ -86,6 +86,18 @@ struct TranslatorVisitor final {
ir.SetVFlag(result.overflow); ir.SetVFlag(result.overflow);
return true; return true;
} }
bool thumb1_ADD_imm(Imm3 imm3, Reg n, Reg d) {
u32 imm32 = imm3 & 0x7;
// ADDS <Rd>, <Rn>, #<imm3>
// Rd can never encode R15.
auto result = ir.AddWithCarry(ir.GetRegister(n), ir.Imm32(imm32), ir.Imm1(0));
ir.SetRegister(d, result.result);
ir.SetNFlag(ir.MostSignificantBit(result.result));
ir.SetZFlag(ir.IsZero(result.result));
ir.SetCFlag(result.carry);
ir.SetVFlag(result.overflow);
return true;
}
bool thumb1_AND_reg(Reg m, Reg d_n) { bool thumb1_AND_reg(Reg m, Reg d_n) {
const Reg d = d_n, n = d_n; const Reg d = d_n, n = d_n;