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Implement thumb1_SUB_imm_t2

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This commit is contained in:
MerryMage 2016-07-08 21:48:55 +08:00
parent 0a1f153805
commit 9e9fa62d5f
3 changed files with 22 additions and 5 deletions
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6
src/frontend/decoder/thumb1.h
View file

@ -56,7 +56,7 @@ private:
};
template <typename V>
static const std::array<Thumb1Matcher<V>, 17> g_thumb1_instruction_table {{
static const std::array<Thumb1Matcher<V>, 18> g_thumb1_instruction_table {{
#define INST(fn, name, bitstring) detail::detail<Thumb1Matcher, u16, 16>::GetMatcher<decltype(fn), fn>(name, bitstring)
@ -67,11 +67,11 @@ static const std::array<Thumb1Matcher<V>, 17> g_thumb1_instruction_table {{
{ INST(&V::thumb1_ADD_reg_t1, "ADD (reg, T1)", "0001100mmmnnnddd") },
{ INST(&V::thumb1_SUB_reg, "SUB (reg)", "0001101mmmnnnddd") },
{ INST(&V::thumb1_ADD_imm_t1, "ADD (imm, T1)", "0001110vvvnnnddd") },
{ INST(&V::thumb1_SUB_imm, "SUB (imm)", "0001111vvvnnnddd") },
{ INST(&V::thumb1_SUB_imm_t1, "SUB (imm, T1)", "0001111vvvnnnddd") },
{ INST(&V::thumb1_MOV_imm, "MOV (imm)", "00100dddvvvvvvvv") },
{ INST(&V::thumb1_CMP_imm, "CMP (imm)", "00101nnnvvvvvvvv") },
{ INST(&V::thumb1_ADD_imm_t2, "ADD (imm, T2)", "00110dddvvvvvvvv") },
//{ INST(&V::thumb1_SUB_ri, "SUB (ri)", "00111dddvvvvvvvv") },
{ INST(&V::thumb1_SUB_imm_t2, "SUB (imm, T2)", "00111dddvvvvvvvv") },
// Data-processing instructions
{ INST(&V::thumb1_AND_reg, "AND (reg)", "0100000000mmmddd") },

6
src/frontend/disassembler_thumb.cpp
View file

@ -126,7 +126,7 @@ public:
return Common::StringFromFormat("adds %s, %s, #%u", RegStr(d), RegStr(n), imm3);
}
std::string thumb1_SUB_imm(Imm3 imm3, Reg n, Reg d) {
std::string thumb1_SUB_imm_t1(Imm3 imm3, Reg n, Reg d) {
return Common::StringFromFormat("subs %s, %s, #%u", RegStr(d), RegStr(n), imm3);
}
@ -142,6 +142,10 @@ public:
return Common::StringFromFormat("adds %s, #%u", RegStr(d_n), imm8);
}
std::string thumb1_SUB_imm_t2(Reg d_n, Imm8 imm8) {
return Common::StringFromFormat("subs %s, #%u", RegStr(d_n), imm8);
}
std::string thumb1_AND_reg(Reg m, Reg d_n) {
return Common::StringFromFormat("ands %s, %s", RegStr(d_n), RegStr(m));
}

15
src/frontend/translate_thumb.cpp
View file

@ -98,7 +98,7 @@ struct TranslatorVisitor final {
ir.SetVFlag(result.overflow);
return true;
}
bool thumb1_SUB_imm(Imm3 imm3, Reg n, Reg d) {
bool thumb1_SUB_imm_t1(Imm3 imm3, Reg n, Reg d) {
u32 imm32 = imm3 & 0x7;
// SUBS <Rd>, <Rn>, #<imm3>
// Rd can never encode R15.
@ -143,6 +143,19 @@ struct TranslatorVisitor final {
ir.SetVFlag(result.overflow);
return true;
}
bool thumb1_SUB_imm_t2(Reg d_n, Imm8 imm8) {
u32 imm32 = imm8 & 0xFF;
Reg d = d_n, n = d_n;
// SUBS <Rd>, <Rn>, #<imm3>
// Rd can never encode R15.
auto result = ir.SubWithCarry(ir.GetRegister(n), ir.Imm32(imm32), ir.Imm1(1));
ir.SetRegister(d, result.result);
ir.SetNFlag(ir.MostSignificantBit(result.result));
ir.SetZFlag(ir.IsZero(result.result));
ir.SetCFlag(result.carry);
ir.SetVFlag(result.overflow);
return true;
}
bool thumb1_AND_reg(Reg m, Reg d_n) {
const Reg d = d_n, n = d_n;