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A64: Implement SQDMULH's vector variant

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Lioncash 2018-09-05 17:14:02 -04:00 committed by MerryMage
parent a0231e5546
commit 9c03311fed
2 changed files with 17 additions and 1 deletions
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2
src/frontend/A64/decoder/a64.inc
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@ -722,7 +722,7 @@ INST(MLA_vec, "MLA (vector)", "0Q001
INST(MUL_vec, "MUL (vector)", "0Q001110zz1mmmmm100111nnnnnddddd")
INST(SMAXP, "SMAXP", "0Q001110zz1mmmmm101001nnnnnddddd")
INST(SMINP, "SMINP", "0Q001110zz1mmmmm101011nnnnnddddd")
//INST(SQDMULH_vec_2, "SQDMULH (vector)", "0Q001110zz1mmmmm101101nnnnnddddd")
INST(SQDMULH_vec_2, "SQDMULH (vector)", "0Q001110zz1mmmmm101101nnnnnddddd")
INST(ADDP_vec, "ADDP (vector)", "0Q001110zz1mmmmm101111nnnnnddddd")
INST(FMAXNM_2, "FMAXNM (vector)", "0Q0011100z1mmmmm110001nnnnnddddd")
INST(FMLA_vec_2, "FMLA (vector)", "0Q0011100z1mmmmm110011nnnnnddddd")

16
src/frontend/A64/translate/impl/simd_three_same.cpp
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@ -422,6 +422,22 @@ bool TranslatorVisitor::SMINP(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
return PairedMinMaxOperation(*this, Q, size, Vm, Vn, Vd, MinMaxOperation::Min, Signedness::Signed);
}
bool TranslatorVisitor::SQDMULH_vec_2(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
if (size == 0b00 || size == 0b11) {
return ReservedValue();
}
const size_t esize = 8 << size.ZeroExtend();
const size_t datasize = Q ? 128 : 64;
const IR::U128 operand1 = V(datasize, Vn);
const IR::U128 operand2 = V(datasize, Vm);
const IR::U128 result = ir.VectorSignedSaturatedDoublingMultiplyReturnHigh(esize, operand1, operand2);
V(datasize, Vd, result);
return true;
}
bool TranslatorVisitor::ADD_vector(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
if (size == 0b11 && !Q) return ReservedValue();
const size_t esize = 8 << size.ZeroExtend<size_t>();