A32: Implement the ARM-mode variant of SEVL

This commit is contained in:
Lioncash 2019-05-03 10:57:26 -04:00 committed by MerryMage
parent e89ca42048
commit 9a097e307f
6 changed files with 12 additions and 1 deletions

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@ -26,6 +26,8 @@ enum class Exception {
UnpredictableInstruction, UnpredictableInstruction,
/// A SEV instruction was executed. The event register of all PEs should be set. /// A SEV instruction was executed. The event register of all PEs should be set.
SendEvent, SendEvent,
/// A SEVL instruction was executed. The event register of the current PE should be set.
SendEventLocal,
/// A WFI instruction was executed. You may now enter a low-power state. /// A WFI instruction was executed. You may now enter a low-power state.
WaitForInterrupt, WaitForInterrupt,
/// A WFE instruction was executed. You may now enter a low-power state if the event register is clear. /// A WFE instruction was executed. You may now enter a low-power state if the event register is clear.

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@ -34,7 +34,7 @@ enum class Exception {
WaitForEvent, WaitForEvent,
/// A SEV instruction was executed. The event register of all PEs should be set. /// A SEV instruction was executed. The event register of all PEs should be set.
SendEvent, SendEvent,
/// A SEV instruction was executed. The event register of the current PE should be set. /// A SEVL instruction was executed. The event register of the current PE should be set.
SendEventLocal, SendEventLocal,
/// A YIELD instruction was executed. /// A YIELD instruction was executed.
Yield, Yield,

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@ -97,6 +97,7 @@ INST(arm_UXTAH, "UXTAH", "cccc01101111nnnnddddrr000111mmmm
INST(arm_PLD_imm, "PLD (imm)", "11110101uz01nnnn1111iiiiiiiiiiii") // v5E for PLD; v7 for PLDW INST(arm_PLD_imm, "PLD (imm)", "11110101uz01nnnn1111iiiiiiiiiiii") // v5E for PLD; v7 for PLDW
INST(arm_PLD_reg, "PLD (reg)", "11110111uz01nnnn1111iiiiitt0mmmm") // v5E for PLD; v7 for PLDW INST(arm_PLD_reg, "PLD (reg)", "11110111uz01nnnn1111iiiiitt0mmmm") // v5E for PLD; v7 for PLDW
INST(arm_SEV, "SEV", "----0011001000001111000000000100") // v6K INST(arm_SEV, "SEV", "----0011001000001111000000000100") // v6K
INST(arm_SEVL, "SEVL", "----0011001000001111000000000101") // v8
INST(arm_WFE, "WFE", "----0011001000001111000000000010") // v6K INST(arm_WFE, "WFE", "----0011001000001111000000000010") // v6K
INST(arm_WFI, "WFI", "----0011001000001111000000000011") // v6K INST(arm_WFI, "WFI", "----0011001000001111000000000011") // v6K
INST(arm_YIELD, "YIELD", "----0011001000001111000000000001") // v6K INST(arm_YIELD, "YIELD", "----0011001000001111000000000001") // v6K

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@ -451,6 +451,9 @@ public:
std::string arm_SEV() { std::string arm_SEV() {
return "sev"; return "sev";
} }
std::string arm_SEVL() {
return "sevl";
}
std::string arm_WFE() { std::string arm_WFE() {
return "wfe"; return "wfe";
} }

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@ -33,6 +33,10 @@ bool ArmTranslatorVisitor::arm_SEV() {
return RaiseException(Exception::SendEvent); return RaiseException(Exception::SendEvent);
} }
bool ArmTranslatorVisitor::arm_SEVL() {
return RaiseException(Exception::SendEventLocal);
}
bool ArmTranslatorVisitor::arm_WFE() { bool ArmTranslatorVisitor::arm_WFE() {
return RaiseException(Exception::WaitForEvent); return RaiseException(Exception::WaitForEvent);
} }

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@ -167,6 +167,7 @@ struct ArmTranslatorVisitor final {
bool arm_PLD_imm(bool add, bool R, Reg n, Imm<12> imm12); bool arm_PLD_imm(bool add, bool R, Reg n, Imm<12> imm12);
bool arm_PLD_reg(bool add, bool R, Reg n, Imm<5> imm5, ShiftType shift, Reg m); bool arm_PLD_reg(bool add, bool R, Reg n, Imm<5> imm5, ShiftType shift, Reg m);
bool arm_SEV(); bool arm_SEV();
bool arm_SEVL();
bool arm_WFE(); bool arm_WFE();
bool arm_WFI(); bool arm_WFI();
bool arm_YIELD(); bool arm_YIELD();