diff --git a/src/frontend/decoder/thumb1.h b/src/frontend/decoder/thumb1.h index e440bb52..89f18f0e 100644 --- a/src/frontend/decoder/thumb1.h +++ b/src/frontend/decoder/thumb1.h @@ -56,7 +56,7 @@ private: }; template -static const std::array, 14> g_thumb1_instruction_table {{ +static const std::array, 15> g_thumb1_instruction_table {{ #define INST(fn, name, bitstring) detail::detail::GetMatcher(name, bitstring) @@ -68,7 +68,7 @@ static const std::array, 14> g_thumb1_instruction_table {{ { INST(&V::thumb1_SUB_reg, "SUB (reg)", "0001101mmmnnnddd") }, { INST(&V::thumb1_ADD_imm, "ADD (imm)", "0001110vvvnnnddd") }, { INST(&V::thumb1_SUB_imm, "SUB (imm)", "0001111vvvnnnddd") }, - //{ INST(&V::thumb1_MOV_ri, "MOV (ri)", "00100dddvvvvvvvv") }, + { INST(&V::thumb1_MOV_imm, "MOV (imm)", "00100dddvvvvvvvv") }, //{ INST(&V::thumb1_CMP_ri, "CMP (ri)", "00101dddvvvvvvvv") }, //{ INST(&V::thumb1_ADD_ri, "ADD (ri)", "00110dddvvvvvvvv") }, //{ INST(&V::thumb1_SUB_ri, "SUB (ri)", "00111dddvvvvvvvv") }, diff --git a/src/frontend/disassembler_thumb.cpp b/src/frontend/disassembler_thumb.cpp index 0b66fe95..d0d95eaf 100644 --- a/src/frontend/disassembler_thumb.cpp +++ b/src/frontend/disassembler_thumb.cpp @@ -130,6 +130,10 @@ public: return Common::StringFromFormat("subs %s, %s, #%u", RegStr(d), RegStr(n), imm3); } + std::string thumb1_MOV_imm(Reg d, Imm8 imm8) { + return Common::StringFromFormat("movs %s, #%u", RegStr(d), imm8); + } + std::string thumb1_AND_reg(Reg m, Reg d_n) { return Common::StringFromFormat("ands %s, %s", RegStr(d_n), RegStr(m)); } diff --git a/src/frontend/translate_thumb.cpp b/src/frontend/translate_thumb.cpp index 68dc47b6..a97d4dea 100644 --- a/src/frontend/translate_thumb.cpp +++ b/src/frontend/translate_thumb.cpp @@ -110,6 +110,16 @@ struct TranslatorVisitor final { ir.SetVFlag(result.overflow); return true; } + bool thumb1_MOV_imm(Reg d, Imm8 imm8) { + u32 imm32 = imm8 & 0xFF; + // MOVS , # + // Rd can never encode R15. + auto result = ir.Imm32(imm32); + ir.SetRegister(d, result); + ir.SetNFlag(ir.MostSignificantBit(result)); + ir.SetZFlag(ir.IsZero(result)); + return true; + } bool thumb1_AND_reg(Reg m, Reg d_n) { const Reg d = d_n, n = d_n;