From 97b5fa173f5d15334cae772db62d465a43602a45 Mon Sep 17 00:00:00 2001 From: MerryMage Date: Sun, 7 Aug 2016 01:41:25 +0100 Subject: [PATCH] VFP: Implement VSUB --- src/backend_x64/emit_x64.cpp | 42 +++++++++++++++++++ src/frontend/decoder/vfp2.h | 2 +- .../disassembler/disassembler_arm.cpp | 4 ++ src/frontend/ir/ir_emitter.cpp | 10 +++++ src/frontend/ir/ir_emitter.h | 2 + src/frontend/ir/opcodes.inc | 2 + .../translate/translate_arm/translate_arm.h | 1 + src/frontend/translate/translate_arm/vfp2.cpp | 19 +++++++++ 8 files changed, 81 insertions(+), 1 deletion(-) diff --git a/src/backend_x64/emit_x64.cpp b/src/backend_x64/emit_x64.cpp index d4e0fd2d..01c12dbc 100644 --- a/src/backend_x64/emit_x64.cpp +++ b/src/backend_x64/emit_x64.cpp @@ -1148,6 +1148,48 @@ void EmitX64::EmitFPAdd64(IR::Block& block, IR::Inst* inst) { } } +void EmitX64::EmitFPSub32(IR::Block& block, IR::Inst* inst) { + IR::Value a = inst->GetArg(0); + IR::Value b = inst->GetArg(1); + + X64Reg result = reg_alloc.UseDefRegister(a, inst, any_xmm); + X64Reg operand = reg_alloc.UseRegister(b, any_xmm); + X64Reg gpr_scratch = reg_alloc.ScratchRegister(any_gpr); + + if (block.location.FPSCR_FTZ()) { + DenormalsAreZero32(code, result, gpr_scratch); + DenormalsAreZero32(code, operand, gpr_scratch); + } + code->SUBSS(result, R(operand)); + if (block.location.FPSCR_FTZ()) { + FlushToZero32(code, result, gpr_scratch); + } + if (block.location.FPSCR_DN()) { + DefaultNaN32(code, routines, result); + } +} + +void EmitX64::EmitFPSub64(IR::Block& block, IR::Inst* inst) { + IR::Value a = inst->GetArg(0); + IR::Value b = inst->GetArg(1); + + X64Reg result = reg_alloc.UseDefRegister(a, inst, any_xmm); + X64Reg operand = reg_alloc.UseRegister(b, any_xmm); + X64Reg gpr_scratch = reg_alloc.ScratchRegister(any_gpr); + + if (block.location.FPSCR_FTZ()) { + DenormalsAreZero64(code, routines, result, gpr_scratch); + DenormalsAreZero64(code, routines, operand, gpr_scratch); + } + code->SUBSD(result, R(operand)); + if (block.location.FPSCR_FTZ()) { + FlushToZero64(code, routines, result, gpr_scratch); + } + if (block.location.FPSCR_DN()) { + DefaultNaN64(code, routines, result); + } +} + void EmitX64::EmitReadMemory8(IR::Block&, IR::Inst* inst) { reg_alloc.HostCall(inst, inst->GetArg(0)); diff --git a/src/frontend/decoder/vfp2.h b/src/frontend/decoder/vfp2.h index 0bae062c..48d49b6c 100644 --- a/src/frontend/decoder/vfp2.h +++ b/src/frontend/decoder/vfp2.h @@ -71,7 +71,7 @@ boost::optional&> DecodeVFP2(u32 instruction) { // VNMUL // VMUL INST(&V::vfp2_VADD, "VADD", "cccc11100D11nnnndddd101zN0M0mmmm"), - // VSUB + INST(&V::vfp2_VSUB, "VSUB", "cccc11100D11nnnndddd101zN1M0mmmm"), // VDIV // Floating-point other instructions diff --git a/src/frontend/disassembler/disassembler_arm.cpp b/src/frontend/disassembler/disassembler_arm.cpp index fbb28d2c..6ce15a65 100644 --- a/src/frontend/disassembler/disassembler_arm.cpp +++ b/src/frontend/disassembler/disassembler_arm.cpp @@ -564,6 +564,10 @@ public: return Common::StringFromFormat("vadd%s.%s %s, %s, %s", CondToString(cond), sz ? "f64" : "f32", FPRegStr(sz, Vd, D).c_str(), FPRegStr(sz, Vn, N).c_str(), FPRegStr(sz, Vm, M).c_str()); } + std::string vfp2_VSUB(Cond cond, bool D, size_t Vn, size_t Vd, bool sz, bool N, bool M, size_t Vm) { + return Common::StringFromFormat("vsub%s.%s %s, %s, %s", CondToString(cond), sz ? "f64" : "f32", FPRegStr(sz, Vd, D).c_str(), FPRegStr(sz, Vn, N).c_str(), FPRegStr(sz, Vm, M).c_str()); + } + std::string vfp2_VABS(Cond cond, bool D, size_t Vd, bool sz, bool M, size_t Vm) { return Common::StringFromFormat("vadd%s.%s %s, %s", CondToString(cond), sz ? "f64" : "f32", FPRegStr(sz, Vd, D).c_str(), FPRegStr(sz, Vm, M).c_str()); } diff --git a/src/frontend/ir/ir_emitter.cpp b/src/frontend/ir/ir_emitter.cpp index 19ca9d06..e2cdd3ee 100644 --- a/src/frontend/ir/ir_emitter.cpp +++ b/src/frontend/ir/ir_emitter.cpp @@ -292,6 +292,16 @@ IR::Value IREmitter::FPAdd64(const IR::Value& a, const IR::Value& b, bool fpscr_ return Inst(IR::Opcode::FPAdd64, {a, b}); } +IR::Value IREmitter::FPSub32(const IR::Value& a, const IR::Value& b, bool fpscr_controlled) { + ASSERT(fpscr_controlled); + return Inst(IR::Opcode::FPSub32, {a, b}); +} + +IR::Value IREmitter::FPSub64(const IR::Value& a, const IR::Value& b, bool fpscr_controlled) { + ASSERT(fpscr_controlled); + return Inst(IR::Opcode::FPSub64, {a, b}); +} + IR::Value IREmitter::ReadMemory8(const IR::Value& vaddr) { return Inst(IR::Opcode::ReadMemory8, {vaddr}); } diff --git a/src/frontend/ir/ir_emitter.h b/src/frontend/ir/ir_emitter.h index 3dfaa057..29298734 100644 --- a/src/frontend/ir/ir_emitter.h +++ b/src/frontend/ir/ir_emitter.h @@ -96,6 +96,8 @@ public: IR::Value FPAbs64(const IR::Value& a); IR::Value FPAdd32(const IR::Value& a, const IR::Value& b, bool fpscr_controlled); IR::Value FPAdd64(const IR::Value& a, const IR::Value& b, bool fpscr_controlled); + IR::Value FPSub32(const IR::Value& a, const IR::Value& b, bool fpscr_controlled); + IR::Value FPSub64(const IR::Value& a, const IR::Value& b, bool fpscr_controlled); IR::Value ReadMemory8(const IR::Value& vaddr); IR::Value ReadMemory16(const IR::Value& vaddr); diff --git a/src/frontend/ir/opcodes.inc b/src/frontend/ir/opcodes.inc index 982cbf51..7f32e794 100644 --- a/src/frontend/ir/opcodes.inc +++ b/src/frontend/ir/opcodes.inc @@ -64,6 +64,8 @@ OPCODE(FPAbs32, T::F32, T::F32 OPCODE(FPAbs64, T::F64, T::F64 ) OPCODE(FPAdd32, T::F32, T::F32, T::F32 ) OPCODE(FPAdd64, T::F64, T::F64, T::F64 ) +OPCODE(FPSub32, T::F32, T::F32, T::F32 ) +OPCODE(FPSub64, T::F64, T::F64, T::F64 ) // Memory access OPCODE(ReadMemory8, T::U8, T::U32 ) diff --git a/src/frontend/translate/translate_arm/translate_arm.h b/src/frontend/translate/translate_arm/translate_arm.h index 6de08443..a1a8d9ab 100644 --- a/src/frontend/translate/translate_arm/translate_arm.h +++ b/src/frontend/translate/translate_arm/translate_arm.h @@ -320,6 +320,7 @@ struct ArmTranslatorVisitor final { // Floating-point three-register data processing instructions bool vfp2_VADD(Cond cond, bool D, size_t Vn, size_t Vd, bool sz, bool N, bool M, size_t Vm); + bool vfp2_VSUB(Cond cond, bool D, size_t Vn, size_t Vd, bool sz, bool N, bool M, size_t Vm); // Floating-point misc instructions bool vfp2_VABS(Cond cond, bool D, size_t Vd, bool sz, bool M, size_t Vm); diff --git a/src/frontend/translate/translate_arm/vfp2.cpp b/src/frontend/translate/translate_arm/vfp2.cpp index 0277f050..ed723314 100644 --- a/src/frontend/translate/translate_arm/vfp2.cpp +++ b/src/frontend/translate/translate_arm/vfp2.cpp @@ -36,6 +36,25 @@ bool ArmTranslatorVisitor::vfp2_VADD(Cond cond, bool D, size_t Vn, size_t Vd, bo return true; } +bool ArmTranslatorVisitor::vfp2_VSUB(Cond cond, bool D, size_t Vn, size_t Vd, bool sz, bool N, bool M, size_t Vm) { + if (ir.current_location.FPSCR_Len() != 1 || ir.current_location.FPSCR_Stride() != 1) + return InterpretThisInstruction(); // TODO: Vectorised floating point instructions + + ExtReg d = ToExtReg(sz, Vd, D); + ExtReg n = ToExtReg(sz, Vn, N); + ExtReg m = ToExtReg(sz, Vm, M); + // VSUB.{F32,F64} <{S,D}d>, <{S,D}n>, <{S,D}m> + if (ConditionPassed(cond)) { + auto a = ir.GetExtendedRegister(n); + auto b = ir.GetExtendedRegister(m); + auto result = sz + ? ir.FPSub64(a, b, true) + : ir.FPSub32(a, b, true); + ir.SetExtendedRegister(d, result); + } + return true; +} + bool ArmTranslatorVisitor::vfp2_VABS(Cond cond, bool D, size_t Vd, bool sz, bool M, size_t Vm) { if (ir.current_location.FPSCR_Len() != 1 || ir.current_location.FPSCR_Stride() != 1) return InterpretThisInstruction(); // TODO: Vectorised floating point instructions