thumb32: Implement LDRD (literal)
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a74843ca17
commit
9757e2353f
3 changed files with 30 additions and 2 deletions
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@ -15,8 +15,8 @@ INST(thumb32_LDMDB, "LDMDB/LDMEA", "1110100100W1nnnniiiiii
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//INST(thumb32_LDREX, "LDREX", "111010000101--------------------")
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INST(thumb32_STRD_imm_1, "STRD (imm)", "11101000U110nnnnttttssssiiiiiiii")
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INST(thumb32_STRD_imm_2, "STRD (imm)", "11101001U1W0nnnnttttssssiiiiiiii")
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//INST(thumb32_LDRD_imm_1, "LDRD (lit)", "11101000-1111111----------------")
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//INST(thumb32_LDRD_imm_2, "LDRD (lit)", "11101001-1-11111----------------")
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INST(thumb32_LDRD_lit_1, "LDRD (lit)", "11101000U1111111ttttssssiiiiiiii")
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INST(thumb32_LDRD_lit_2, "LDRD (lit)", "11101001U1W11111ttttssssiiiiiiii")
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//INST(thumb32_LDRD_imm_1, "LDRD (imm)", "11101000-111--------------------")
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//INST(thumb32_LDRD_imm_2, "LDRD (imm)", "11101001-1-1--------------------")
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//INST(thumb32_STREXB, "STREXB", "111010001100------------0100----")
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@ -39,6 +39,24 @@ static bool TableBranch(ThumbTranslatorVisitor& v, Reg n, Reg m, bool half) {
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return false;
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}
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static bool LoadDualLiteral(ThumbTranslatorVisitor& v, bool U, bool W, Reg t, Reg t2, Imm<8> imm8) {
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if (t == Reg::PC || t2 == Reg::PC || t == t2) {
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return v.UnpredictableInstruction();
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}
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if (W) {
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return v.UnpredictableInstruction();
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}
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const auto imm = imm8.ZeroExtend() << 2;
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const auto address_1 = U ? v.ir.Add(v.ir.Imm32(v.ir.AlignPC(4)), v.ir.Imm32(imm))
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: v.ir.Sub(v.ir.Imm32(v.ir.AlignPC(4)), v.ir.Imm32(imm));
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const auto address_2 = v.ir.Add(address_1, v.ir.Imm32(4));
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v.ir.SetRegister(t, v.ir.ReadMemory32(address_1));
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v.ir.SetRegister(t2, v.ir.ReadMemory32(address_2));
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return true;
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}
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static bool StoreDual(ThumbTranslatorVisitor& v, bool P, bool U, bool W, Reg n, Reg t, Reg t2, Imm<8> imm8) {
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if (W && (n == t || n == t2)) {
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return v.UnpredictableInstruction();
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@ -67,6 +85,14 @@ static bool StoreDual(ThumbTranslatorVisitor& v, bool P, bool U, bool W, Reg n,
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return true;
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}
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bool ThumbTranslatorVisitor::thumb32_LDRD_lit_1(bool U, Reg t, Reg t2, Imm<8> imm8) {
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return LoadDualLiteral(*this, U, true, t, t2, imm8);
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}
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bool ThumbTranslatorVisitor::thumb32_LDRD_lit_2(bool U, bool W, Reg t, Reg t2, Imm<8> imm8) {
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return LoadDualLiteral(*this, U, W, t, t2, imm8);
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}
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bool ThumbTranslatorVisitor::thumb32_STRD_imm_1(bool U, Reg n, Reg t, Reg t2, Imm<8> imm8) {
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return StoreDual(*this, false, U, true, n, t, t2, imm8);
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}
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@ -180,6 +180,8 @@ struct ThumbTranslatorVisitor final {
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bool thumb32_STMDB(bool W, Reg n, Imm<15> reg_list);
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// thumb32 load/store dual, load/store exclusive, table branch instructions
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bool thumb32_LDRD_lit_1(bool U, Reg t, Reg t2, Imm<8> imm8);
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bool thumb32_LDRD_lit_2(bool U, bool W, Reg t, Reg t2, Imm<8> imm8);
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bool thumb32_STRD_imm_1(bool U, Reg n, Reg t, Reg t2, Imm<8> imm8);
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bool thumb32_STRD_imm_2(bool U, bool W, Reg n, Reg t, Reg t2, Imm<8> imm8);
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bool thumb32_TBB(Reg n, Reg m);
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