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A32: Implement ASIMD VQSHL/VQSHLU (immediate)

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Lioncash 2020-06-21 13:49:04 -04:00 committed by merry
parent 3557576ece
commit 95919594d1
3 changed files with 41 additions and 1 deletions
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2
src/frontend/A32/decoder/asimd.inc
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@ -70,7 +70,7 @@ INST(asimd_VRSRA, "VRSRA", "1111001U1Diiiiiidddd001
INST(asimd_VSRI, "VSRI", "111100111Diiiiiidddd0100LQM1mmmm") // ASIMD
INST(asimd_VSHL, "VSHL", "111100101Diiiiiidddd0101LQM1mmmm") // ASIMD
INST(asimd_VSLI, "VSLI", "111100111Diiiiiidddd0101LQM1mmmm") // ASIMD
//INST(asimd_VQSHL, "VQSHL" , "1111001U1-vvv-------011xLB-1----") // ASIMD
INST(asimd_VQSHL, "VQSHL" , "1111001U1Diiiiiidddd011oLQM1mmmm") // ASIMD
INST(asimd_VSHRN, "VSHRN", "111100101Diiiiiidddd100000M1mmmm") // ASIMD
//INST(asimd_VRSHRN, "VRSHRN", "111100101-vvv-------100001-1----") // ASIMD
//INST(asimd_VQSHRUN, "VQSHRUN", "111100111-vvv-------100000-1----") // ASIMD

39
src/frontend/A32/translate/impl/asimd_two_regs_shift.cpp
View file

@ -216,6 +216,45 @@ bool ArmTranslatorVisitor::asimd_VSLI(bool D, size_t imm6, size_t Vd, bool L, bo
return true;
}
bool ArmTranslatorVisitor::asimd_VQSHL(bool U, bool D, size_t imm6, size_t Vd, bool op, bool L, bool Q, bool M, size_t Vm) {
if (Q && (Common::Bit<0>(Vd) || Common::Bit<0>(Vm))) {
return UndefinedInstruction();
}
if (!U && !op) {
return UndefinedInstruction();
}
// Technically just a related encoding (One register and modified immediate instructions)
if (!L && Common::Bits<3, 5>(imm6) == 0) {
ASSERT_FALSE();
}
const auto d = ToVector(Q, Vd, D);
const auto m = ToVector(Q, Vm, M);
const auto result = [&] {
const auto reg_m = ir.GetVector(m);
const auto [esize, shift_amount] = ElementSizeAndShiftAmount(false, L, imm6);
const IR::U128 shift_vec = ir.VectorBroadcast(esize, I(esize, shift_amount));
if (U) {
if (op) {
return ir.VectorUnsignedSaturatedShiftLeft(esize, reg_m, shift_vec);
}
return ir.VectorSignedSaturatedShiftLeftUnsigned(esize, reg_m, shift_vec);
}
if (op) {
return ir.VectorSignedSaturatedShiftLeft(esize, reg_m, shift_vec);
}
return IR::U128{};
}();
ir.SetVector(d, result);
return true;
}
bool ArmTranslatorVisitor::asimd_VSHL(bool D, size_t imm6, size_t Vd, bool L, bool Q, bool M, size_t Vm) {
if (Q && (Common::Bit<0>(Vd) || Common::Bit<0>(Vm))) {
return UndefinedInstruction();

1
src/frontend/A32/translate/impl/translate_arm.h
View file

@ -508,6 +508,7 @@ struct ArmTranslatorVisitor final {
bool asimd_VSRI(bool D, size_t imm6, size_t Vd, bool L, bool Q, bool M, size_t Vm);
bool asimd_VSHL(bool D, size_t imm6, size_t Vd, bool L, bool Q, bool M, size_t Vm);
bool asimd_VSLI(bool D, size_t imm6, size_t Vd, bool L, bool Q, bool M, size_t Vm);
bool asimd_VQSHL(bool U, bool D, size_t imm6, size_t Vd, bool op, bool L, bool Q, bool M, size_t Vm);
bool asimd_VSHRN(bool D, size_t imm6, size_t Vd, bool M, size_t Vm);
bool asimd_VQRSHRUN(bool D, size_t imm6, size_t Vd, bool M, size_t Vm);
bool asimd_VQRSHRN(bool U, bool D, size_t imm6, size_t Vd, bool M, size_t Vm);