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translate_arm/status_register_access: Invert conditionals where applicable

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Lioncash 2019-03-01 02:11:05 -05:00 committed by MerryMage
parent c6aa1a708a
commit 9514e3602e
1 changed files with 74 additions and 50 deletions
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56
src/frontend/A32/translate/translate_arm/status_register_access.cpp
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@ -10,34 +10,47 @@
namespace Dynarmic::A32 {
// CPS<effect> <iflags>{, #<mode>}
// CPS #<mode>
bool ArmTranslatorVisitor::arm_CPS() {
return InterpretThisInstruction();
}
// MRS<c> <Rd>, <spec_reg>
bool ArmTranslatorVisitor::arm_MRS(Cond cond, Reg d) {
if (d == Reg::PC)
if (d == Reg::PC) {
return UnpredictableInstruction();
// MRS <Rd>, APSR
if (ConditionPassed(cond)) {
ir.SetRegister(d, ir.GetCpsr());
}
if (!ConditionPassed(cond)) {
return true;
}
ir.SetRegister(d, ir.GetCpsr());
return true;
}
// MSR<c> <spec_reg>, #<const>
bool ArmTranslatorVisitor::arm_MSR_imm(Cond cond, int mask, int rotate, Imm8 imm8) {
ASSERT_MSG(mask != 0, "Decode error");
if (!ConditionPassed(cond)) {
return true;
}
const bool write_nzcvq = Common::Bit<3>(mask);
const bool write_g = Common::Bit<2>(mask);
const bool write_e = Common::Bit<1>(mask);
const u32 imm32 = ArmExpandImm(rotate, imm8);
ASSERT_MSG(mask != 0, "Decode error");
// MSR <spec_reg>, #<imm32>
if (ConditionPassed(cond)) {
if (write_nzcvq) {
ir.SetCpsrNZCVQ(ir.Imm32(imm32 & 0xF8000000));
}
if (write_g) {
ir.SetGEFlagsCompressed(ir.Imm32(imm32 & 0x000F0000));
}
if (write_e) {
const bool E = (imm32 & 0x00000200) != 0;
if (E != ir.current_location.EFlag()) {
@ -45,25 +58,34 @@ bool ArmTranslatorVisitor::arm_MSR_imm(Cond cond, int mask, int rotate, Imm8 imm
return false;
}
}
}
return true;
}
// MSR<c> <spec_reg>, <Rn>
bool ArmTranslatorVisitor::arm_MSR_reg(Cond cond, int mask, Reg n) {
if (mask == 0) {
return UnpredictableInstruction();
}
if (n == Reg::PC) {
return UnpredictableInstruction();
}
if (!ConditionPassed(cond)) {
return true;
}
const bool write_nzcvq = Common::Bit<3>(mask);
const bool write_g = Common::Bit<2>(mask);
const bool write_e = Common::Bit<1>(mask);
if (mask == 0)
return UnpredictableInstruction();
if (n == Reg::PC)
return UnpredictableInstruction();
// MSR <spec_reg>, #<imm32>
if (ConditionPassed(cond)) {
const auto value = ir.GetRegister(n);
if (!write_e) {
if (write_nzcvq) {
ir.SetCpsrNZCVQ(ir.And(value, ir.Imm32(0xF8000000)));
}
if (write_g) {
ir.SetGEFlagsCompressed(ir.And(value, ir.Imm32(0x000F0000)));
}
@ -77,20 +99,22 @@ bool ArmTranslatorVisitor::arm_MSR_reg(Cond cond, int mask, Reg n) {
ir.SetTerm(IR::Term::CheckHalt{IR::Term::PopRSBHint{}});
return false;
}
}
return true;
}
// RFE{<amode>} <Rn>{!}
bool ArmTranslatorVisitor::arm_RFE() {
return InterpretThisInstruction();
}
// SETEND <endian_specifier>
bool ArmTranslatorVisitor::arm_SETEND(bool E) {
// SETEND {BE,LE}
ir.SetTerm(IR::Term::LinkBlock{ir.current_location.AdvancePC(4).SetEFlag(E)});
return false;
}
// SRS{<amode>} SP{!}, #<mode>
bool ArmTranslatorVisitor::arm_SRS() {
return InterpretThisInstruction();
}