diff --git a/src/dynarmic/backend/arm64/a32_jitstate.h b/src/dynarmic/backend/arm64/a32_jitstate.h
index 875d44b6..2c240ab1 100644
--- a/src/dynarmic/backend/arm64/a32_jitstate.h
+++ b/src/dynarmic/backend/arm64/a32_jitstate.h
@@ -16,9 +16,9 @@ namespace Dynarmic::Backend::Arm64 {
 
 struct A32JitState {
     u32 cpsr_nzcv = 0;
-    u32 cpsr_ge = 0;
-    u32 cpsr_jaifm = 0;
     u32 cpsr_q = 0;
+    u32 cpsr_jaifm = 0;
+    u32 cpsr_ge = 0;
 
     std::array<u32, 16> regs{};
 
diff --git a/src/dynarmic/backend/arm64/emit_arm64_a32.cpp b/src/dynarmic/backend/arm64/emit_arm64_a32.cpp
index cb73edec..2f7efd16 100644
--- a/src/dynarmic/backend/arm64/emit_arm64_a32.cpp
+++ b/src/dynarmic/backend/arm64/emit_arm64_a32.cpp
@@ -224,10 +224,10 @@ void EmitIR<IR::Opcode::A32GetCpsr>(oaknut::CodeGenerator& code, EmitContext& ct
     auto Wcpsr = ctx.reg_alloc.WriteW(inst);
     RegAlloc::Realize(Wcpsr);
 
-    static_assert(offsetof(A32JitState, cpsr_jaifm) + sizeof(u32) == offsetof(A32JitState, cpsr_q));
+    static_assert(offsetof(A32JitState, cpsr_nzcv) + sizeof(u32) == offsetof(A32JitState, cpsr_q));
 
-    code.LDR(Wcpsr, Xstate, offsetof(A32JitState, cpsr_nzcv));
-    code.LDP(Wscratch0, Wscratch1, Xstate, offsetof(A32JitState, cpsr_jaifm));
+    code.LDP(Wscratch0, Wscratch1, Xstate, offsetof(A32JitState, cpsr_nzcv));
+    code.LDR(Wcpsr, Xstate, offsetof(A32JitState, cpsr_jaifm));
     code.ORR(Wcpsr, Wcpsr, Wscratch0);
     code.ORR(Wcpsr, Wcpsr, Wscratch1);