From 93ed3441b7057e38ca9d8668b93045bfa192f8f6 Mon Sep 17 00:00:00 2001 From: Lioncash Date: Mon, 15 Jun 2020 22:17:33 -0400 Subject: [PATCH] A32: Implement ASIMD VCLS/VCLZ/VCNT --- src/frontend/A32/decoder/asimd.inc | 6 +- .../translate/impl/asimd_two_regs_misc.cpp | 75 +++++++++++++++++++ .../A32/translate/impl/translate_arm.h | 3 + 3 files changed, 81 insertions(+), 3 deletions(-) diff --git a/src/frontend/A32/decoder/asimd.inc b/src/frontend/A32/decoder/asimd.inc index a53c2c09..124a795e 100644 --- a/src/frontend/A32/decoder/asimd.inc +++ b/src/frontend/A32/decoder/asimd.inc @@ -80,9 +80,9 @@ INST(asimd_VQSUB, "VQSUB", "1111001U0Dzznnnndddd001 //INST(asimd_VREV32, "VREV32", "111100111-11--00----00001x-0----") // ASIMD //INST(asimd_VREV16, "VREV16", "111100111-11--00----00010x-0----") // ASIMD //INST(asimd_VPADDL, "VPADDL", "111100111-11--00----0010xx-0----") // ASIMD -//INST(asimd_VCLS, "VCLS", "111100111-11--00----01000x-0----") // ASIMD -//INST(asimd_VCLZ, "VCLZ", "111100111-11--00----01001x-0----") // ASIMD -//INST(asimd_VCNT, "VCNT", "111100111-11--00----01010x-0----") // ASIMD +INST(asimd_VCLS, "VCLS", "111100111D11zz00dddd01000QM0mmmm") // ASIMD +INST(asimd_VCLZ, "VCLZ", "111100111D11zz00dddd01001QM0mmmm") // ASIMD +INST(asimd_VCNT, "VCNT", "111100111D11zz00dddd01010QM0mmmm") // ASIMD //INST(asimd_VMVN_reg, "VMVN_reg", "111100111-11--00----01011x-0----") // ASIMD //INST(asimd_VPADAL, "VPADAL", "111100111-11--00----0110xx-0----") // ASIMD //INST(asimd_VQABS, "VQABS", "111100111-11--00----01110x-0----") // ASIMD diff --git a/src/frontend/A32/translate/impl/asimd_two_regs_misc.cpp b/src/frontend/A32/translate/impl/asimd_two_regs_misc.cpp index 6a00b1e0..944b2d44 100644 --- a/src/frontend/A32/translate/impl/asimd_two_regs_misc.cpp +++ b/src/frontend/A32/translate/impl/asimd_two_regs_misc.cpp @@ -9,6 +9,81 @@ namespace Dynarmic::A32 { +bool ArmTranslatorVisitor::asimd_VCLS(bool D, size_t sz, size_t Vd, bool Q, bool M, size_t Vm) { + if (sz == 0b11) { + return UndefinedInstruction(); + } + + if (Q && (Common::Bit<0>(Vd) || Common::Bit<0>(Vm))) { + return UndefinedInstruction(); + } + + const auto d = ToVector(Q, Vd, D); + const auto m = ToVector(Q, Vm, M); + const auto result = [this, m, sz] { + const auto reg_m = ir.GetVector(m); + const size_t esize = 8U << sz; + const auto one = [this, esize]() -> IR::UAny { + switch (esize) { + case 8: + return ir.Imm8(1); + case 16: + return ir.Imm16(1); + default: + return ir.Imm32(1); + } + }(); + + const auto shifted = ir.VectorArithmeticShiftRight(esize, reg_m, static_cast(esize)); + const auto xored = ir.VectorEor(reg_m, shifted); + const auto clz = ir.VectorCountLeadingZeros(esize, xored); + return ir.VectorSub(esize, clz, ir.VectorBroadcast(esize, one)); + }(); + + ir.SetVector(d, result); + return true; +} + +bool ArmTranslatorVisitor::asimd_VCLZ(bool D, size_t sz, size_t Vd, bool Q, bool M, size_t Vm) { + if (sz == 0b11) { + return UndefinedInstruction(); + } + + if (Q && (Common::Bit<0>(Vd) || Common::Bit<0>(Vm))) { + return UndefinedInstruction(); + } + + const auto d = ToVector(Q, Vd, D); + const auto m = ToVector(Q, Vm, M); + const auto result = [this, m, sz] { + const auto reg_m = ir.GetVector(m); + const size_t esize = 8U << sz; + + return ir.VectorCountLeadingZeros(esize, reg_m); + }(); + + ir.SetVector(d, result); + return true; +} + +bool ArmTranslatorVisitor::asimd_VCNT(bool D, size_t sz, size_t Vd, bool Q, bool M, size_t Vm) { + if (sz != 0b00) { + return UndefinedInstruction(); + } + + if (Q && (Common::Bit<0>(Vd) || Common::Bit<0>(Vm))) { + return UndefinedInstruction(); + } + + const auto d = ToVector(Q, Vd, D); + const auto m = ToVector(Q, Vm, M); + const auto reg_m = ir.GetVector(m); + const auto result = ir.VectorPopulationCount(reg_m); + + ir.SetVector(d, result); + return true; +} + bool ArmTranslatorVisitor::asimd_VNEG(bool D, size_t sz, size_t Vd, bool F, bool Q, bool M, size_t Vm) { if (sz == 0b11 || (F && sz != 0b10)) { return UndefinedInstruction(); diff --git a/src/frontend/A32/translate/impl/translate_arm.h b/src/frontend/A32/translate/impl/translate_arm.h index 39f214f9..5a679f04 100644 --- a/src/frontend/A32/translate/impl/translate_arm.h +++ b/src/frontend/A32/translate/impl/translate_arm.h @@ -449,6 +449,9 @@ struct ArmTranslatorVisitor final { bool asimd_VQSUB(bool U, bool D, size_t sz, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm); // Advanced SIMD two register, miscellaneous + bool asimd_VCLS(bool D, size_t sz, size_t Vd, bool Q, bool M, size_t Vm); + bool asimd_VCLZ(bool D, size_t sz, size_t Vd, bool Q, bool M, size_t Vm); + bool asimd_VCNT(bool D, size_t sz, size_t Vd, bool Q, bool M, size_t Vm); bool asimd_VNEG(bool D, size_t sz, size_t Vd, bool F, bool Q, bool M, size_t Vm); bool asimd_VSWP(bool D, size_t Vd, bool Q, bool M, size_t Vm);