diff --git a/src/backend_x64/emit_x64.cpp b/src/backend_x64/emit_x64.cpp index 90e57846..ae1db333 100644 --- a/src/backend_x64/emit_x64.cpp +++ b/src/backend_x64/emit_x64.cpp @@ -436,6 +436,37 @@ void EmitX64::EmitAddWithCarry(IR::Value* value_) { } } +void EmitX64::EmitSubWithCarry(IR::Value* value_) { + auto value = reinterpret_cast(value_); + auto carry_inst = FindUseWithOpcode(value, IR::Opcode::GetCarryFromOp); + auto overflow_inst = FindUseWithOpcode(value, IR::Opcode::GetOverflowFromOp); + + X64Reg addend = reg_alloc.UseRegister(value->GetArg(1).get()); + X64Reg result = reg_alloc.UseDefRegister(value->GetArg(0).get(), value); + X64Reg carry = carry_inst + ? reg_alloc.UseDefRegister(value->GetArg(2).get(), carry_inst) + : reg_alloc.UseRegister(value->GetArg(2).get()); + X64Reg overflow = overflow_inst + ? reg_alloc.DefRegister(overflow_inst) + : X64Reg::INVALID_REG; + + // TODO: Consider using LEA. + // Note that x64 CF is inverse of what the ARM carry flag is here. + + code->BT(32, R(carry), Imm8(0)); + code->CMC(); + code->SBB(32, R(result), R(addend)); + + if (carry_inst) { + inhibit_emission.insert(carry_inst); + code->SETcc(Gen::CC_NC, R(carry)); + } + if (overflow_inst) { + inhibit_emission.insert(overflow_inst); + code->SETcc(Gen::CC_O, R(overflow)); + } +} + void EmitX64::EmitAnd(IR::Value* value_) { auto value = reinterpret_cast(value_); diff --git a/src/backend_x64/emit_x64.h b/src/backend_x64/emit_x64.h index 81d4d037..92625aae 100644 --- a/src/backend_x64/emit_x64.h +++ b/src/backend_x64/emit_x64.h @@ -53,6 +53,7 @@ public: void EmitLogicalShiftRight(IR::Value* value); void EmitArithmeticShiftRight(IR::Value* value); void EmitAddWithCarry(IR::Value* value); + void EmitSubWithCarry(IR::Value* value); void EmitAnd(IR::Value* value); void EmitEor(IR::Value* value); diff --git a/src/frontend/decoder/thumb1.h b/src/frontend/decoder/thumb1.h index 688c5588..d1814109 100644 --- a/src/frontend/decoder/thumb1.h +++ b/src/frontend/decoder/thumb1.h @@ -56,7 +56,7 @@ private: }; template -static const std::array, 11> g_thumb1_instruction_table {{ +static const std::array, 12> g_thumb1_instruction_table {{ #define INST(fn, name, bitstring) detail::detail::GetMatcher(name, bitstring) @@ -65,7 +65,7 @@ static const std::array, 11> g_thumb1_instruction_table {{ { INST(&V::thumb1_LSR_imm, "LSR (imm)", "00001vvvvvmmmddd") }, { INST(&V::thumb1_ASR_imm, "ASR (imm)", "00010vvvvvmmmddd") }, { INST(&V::thumb1_ADD_reg_t1, "ADD (reg, T1)", "0001100mmmnnnddd") }, - //{ INST(&V::thumb1_SUB_rrr, "SUB (rrr)", "0001101mmmnnnddd") }, + { INST(&V::thumb1_SUB_reg, "SUB (reg)", "0001101mmmnnnddd") }, //{ INST(&V::thumb1_ADD_rri, "ADD (rri)", "0001110mmmnnnddd") }, //{ INST(&V::thumb1_SUB_rri, "SUB (rri)", "0001111mmmnnnddd") }, //{ INST(&V::thumb1_MOV_ri, "MOV (ri)", "00100dddvvvvvvvv") }, diff --git a/src/frontend/disassembler_thumb.cpp b/src/frontend/disassembler_thumb.cpp index 5c8774a2..7a464455 100644 --- a/src/frontend/disassembler_thumb.cpp +++ b/src/frontend/disassembler_thumb.cpp @@ -118,6 +118,10 @@ public: return Common::StringFromFormat("adds %s, %s, %s", RegStr(d), RegStr(n), RegStr(m)); } + std::string thumb1_SUB_reg(Reg m, Reg n, Reg d) { + return Common::StringFromFormat("subs %s, %s, %s", RegStr(d), RegStr(n), RegStr(m)); + } + std::string thumb1_AND_reg(Reg m, Reg d_n) { return Common::StringFromFormat("ands %s, %s", RegStr(d_n), RegStr(m)); } diff --git a/src/frontend/ir/opcodes.inc b/src/frontend/ir/opcodes.inc index aea9ffeb..fa659eb5 100644 --- a/src/frontend/ir/opcodes.inc +++ b/src/frontend/ir/opcodes.inc @@ -30,5 +30,6 @@ OPCODE(LogicalShiftLeft, T::U32, T::U32, T::U8, OPCODE(LogicalShiftRight, T::U32, T::U32, T::U8, T::U1 ) OPCODE(ArithmeticShiftRight, T::U32, T::U32, T::U8, T::U1 ) OPCODE(AddWithCarry, T::U32, T::U32, T::U32, T::U1 ) +OPCODE(SubWithCarry, T::U32, T::U32, T::U32, T::U1 ) OPCODE(And, T::U32, T::U32, T::U32 ) OPCODE(Eor, T::U32, T::U32, T::U32 ) diff --git a/src/frontend/ir_emitter.cpp b/src/frontend/ir_emitter.cpp index 0aeff43b..f78dce19 100644 --- a/src/frontend/ir_emitter.cpp +++ b/src/frontend/ir_emitter.cpp @@ -106,6 +106,14 @@ IREmitter::ResultAndCarryAndOverflow IREmitter::AddWithCarry(IR::ValuePtr a, IR: return {result, carry_out, overflow}; } +IREmitter::ResultAndCarryAndOverflow IREmitter::SubWithCarry(IR::ValuePtr a, IR::ValuePtr b, IR::ValuePtr carry_in) { + // This is equivalent to AddWithCarry(a, Not(b), carry_in). + auto result = Inst(IR::Opcode::SubWithCarry, {a, b, carry_in}); + auto carry_out = Inst(IR::Opcode::GetCarryFromOp, {result}); + auto overflow = Inst(IR::Opcode::GetOverflowFromOp, {result}); + return {result, carry_out, overflow}; +} + IR::ValuePtr IREmitter::And(IR::ValuePtr a, IR::ValuePtr b) { return Inst(IR::Opcode::And, {a, b}); } diff --git a/src/frontend/ir_emitter.h b/src/frontend/ir_emitter.h index 254b8086..b550dc77 100644 --- a/src/frontend/ir_emitter.h +++ b/src/frontend/ir_emitter.h @@ -56,6 +56,7 @@ public: ResultAndCarry LogicalShiftRight(IR::ValuePtr value_in, IR::ValuePtr shift_amount, IR::ValuePtr carry_in); ResultAndCarry ArithmeticShiftRight(IR::ValuePtr value_in, IR::ValuePtr shift_amount, IR::ValuePtr carry_in); ResultAndCarryAndOverflow AddWithCarry(IR::ValuePtr a, IR::ValuePtr b, IR::ValuePtr carry_in); + ResultAndCarryAndOverflow SubWithCarry(IR::ValuePtr a, IR::ValuePtr b, IR::ValuePtr carry_in); IR::ValuePtr And(IR::ValuePtr a, IR::ValuePtr b); IR::ValuePtr Eor(IR::ValuePtr a, IR::ValuePtr b); diff --git a/src/frontend/translate_thumb.cpp b/src/frontend/translate_thumb.cpp index ce618469..be83fa40 100644 --- a/src/frontend/translate_thumb.cpp +++ b/src/frontend/translate_thumb.cpp @@ -75,6 +75,17 @@ struct TranslatorVisitor final { ir.SetVFlag(result.overflow); return true; } + bool thumb1_SUB_reg(Reg m, Reg n, Reg d) { + // SUBS , , + // Note that it is not possible to encode Rd == R15. + auto result = ir.SubWithCarry(ir.GetRegister(n), ir.GetRegister(m), ir.Imm1(1)); + ir.SetRegister(d, result.result); + ir.SetNFlag(ir.MostSignificantBit(result.result)); + ir.SetZFlag(ir.IsZero(result.result)); + ir.SetCFlag(result.carry); + ir.SetVFlag(result.overflow); + return true; + } bool thumb1_AND_reg(Reg m, Reg d_n) { const Reg d = d_n, n = d_n;