From 8d1b9f32cafdd6eed318caa20031e20debc99d54 Mon Sep 17 00:00:00 2001 From: MerryMage Date: Mon, 22 Aug 2016 23:40:30 +0100 Subject: [PATCH] Standardize indentation of switch statments --- src/backend_x64/emit_x64.cpp | 232 +++++++++--------- src/backend_x64/reg_alloc.cpp | 22 +- .../disassembler/disassembler_arm.cpp | 56 ++--- src/frontend/ir/basic_block.cpp | 24 +- src/frontend/ir/microinstruction.cpp | 32 +-- src/frontend/translate/translate_arm.cpp | 42 ++-- .../translate/translate_arm/extension.cpp | 22 +- .../translate/translate_arm/load_store.cpp | 16 +- src/ir_opt/dead_code_elimination_pass.cpp | 81 +++--- src/ir_opt/get_set_elimination_pass.cpp | 112 ++++----- tests/arm/fuzz_arm.cpp | 80 +++--- tests/arm/fuzz_thumb.cpp | 20 +- 12 files changed, 370 insertions(+), 369 deletions(-) diff --git a/src/backend_x64/emit_x64.cpp b/src/backend_x64/emit_x64.cpp index fe7825be..4779afe0 100644 --- a/src/backend_x64/emit_x64.cpp +++ b/src/backend_x64/emit_x64.cpp @@ -44,12 +44,12 @@ static OpArg MJitStateCpsr() { static IR::Inst* FindUseWithOpcode(IR::Inst* inst, IR::Opcode opcode) { switch (opcode) { - case IR::Opcode::GetCarryFromOp: - return inst->carry_inst; - case IR::Opcode::GetOverflowFromOp: - return inst->overflow_inst; - default: - break; + case IR::Opcode::GetCarryFromOp: + return inst->carry_inst; + case IR::Opcode::GetOverflowFromOp: + return inst->overflow_inst; + default: + break; } ASSERT_MSG(false, "unreachable"); @@ -77,16 +77,16 @@ EmitX64::BlockDescriptor EmitX64::Emit(const Arm::LocationDescriptor descriptor, // Call the relevant Emit* member function. switch (inst->GetOpcode()) { -#define OPCODE(name, type, ...) \ - case IR::Opcode::name: \ - EmitX64::Emit##name(block, inst); \ - break; +#define OPCODE(name, type, ...) \ + case IR::Opcode::name: \ + EmitX64::Emit##name(block, inst); \ + break; #include "frontend/ir/opcodes.inc" #undef OPCODE - default: - ASSERT_MSG(false, "Invalid opcode %zu", static_cast(inst->GetOpcode())); - break; + default: + ASSERT_MSG(false, "Invalid opcode %zu", static_cast(inst->GetOpcode())); + break; } reg_alloc.EndOfAllocScope(); @@ -1539,109 +1539,109 @@ static CCFlags EmitCond(BlockOfCode* code, Arm::Cond cond) { CCFlags cc; switch (cond) { - case Arm::Cond::EQ: //z - ZFlag(RAX); - code->CMP(8, R(RAX), Imm8(0)); - cc = CC_NE; - break; - case Arm::Cond::NE: //!z - ZFlag(RAX); - code->CMP(8, R(RAX), Imm8(0)); - cc = CC_E; - break; - case Arm::Cond::CS: //c - CFlag(RBX); - code->CMP(8, R(RBX), Imm8(0)); - cc = CC_NE; - break; - case Arm::Cond::CC: //!c - CFlag(RBX); - code->CMP(8, R(RBX), Imm8(0)); - cc = CC_E; - break; - case Arm::Cond::MI: //n - NFlag(RCX); - code->CMP(8, R(RCX), Imm8(0)); - cc = CC_NE; - break; - case Arm::Cond::PL: //!n - NFlag(RCX); - code->CMP(8, R(RCX), Imm8(0)); - cc = CC_E; - break; - case Arm::Cond::VS: //v - VFlag(RDX); - code->CMP(8, R(RDX), Imm8(0)); - cc = CC_NE; - break; - case Arm::Cond::VC: //!v - VFlag(RDX); - code->CMP(8, R(RDX), Imm8(0)); - cc = CC_E; - break; - case Arm::Cond::HI: { //c & !z - const X64Reg tmp = RSI; - ZFlag(RAX); - code->MOVZX(64, 8, tmp, R(RAX)); - CFlag(RBX); - code->CMP(8, R(RBX), R(tmp)); - cc = CC_A; - break; - } - case Arm::Cond::LS: { //!c | z - const X64Reg tmp = RSI; - ZFlag(RAX); - code->MOVZX(64, 8, tmp, R(RAX)); - CFlag(RBX); - code->CMP(8, R(RBX), R(tmp)); - cc = CC_BE; - break; - } - case Arm::Cond::GE: { // n == v - const X64Reg tmp = RSI; - VFlag(RDX); - code->MOVZX(64, 8, tmp, R(RDX)); - NFlag(RCX); - code->CMP(8, R(RCX), R(tmp)); - cc = CC_E; - break; - } - case Arm::Cond::LT: { // n != v - const X64Reg tmp = RSI; - VFlag(RDX); - code->MOVZX(64, 8, tmp, R(RDX)); - NFlag(RCX); - code->CMP(8, R(RCX), R(tmp)); - cc = CC_NE; - break; - } - case Arm::Cond::GT: { // !z & (n == v) - const X64Reg tmp = RSI; - NFlag(RCX); - code->MOVZX(64, 8, tmp, R(RCX)); - VFlag(RDX); - code->XOR(8, R(tmp), R(RDX)); - ZFlag(RAX); - code->OR(8, R(tmp), R(RAX)); - code->TEST(8, R(tmp), R(tmp)); - cc = CC_Z; - break; - } - case Arm::Cond::LE: { // z | (n != v) - X64Reg tmp = RSI; - NFlag(RCX); - code->MOVZX(64, 8, tmp, R(RCX)); - VFlag(RDX); - code->XOR(8, R(tmp), R(RDX)); - ZFlag(RAX); - code->OR(8, R(tmp), R(RAX)); - code->TEST(8, R(tmp), R(tmp)); - cc = CC_NZ; - break; - } - default: - ASSERT_MSG(0, "Unknown cond %zu", static_cast(cond)); - break; + case Arm::Cond::EQ: //z + ZFlag(RAX); + code->CMP(8, R(RAX), Imm8(0)); + cc = CC_NE; + break; + case Arm::Cond::NE: //!z + ZFlag(RAX); + code->CMP(8, R(RAX), Imm8(0)); + cc = CC_E; + break; + case Arm::Cond::CS: //c + CFlag(RBX); + code->CMP(8, R(RBX), Imm8(0)); + cc = CC_NE; + break; + case Arm::Cond::CC: //!c + CFlag(RBX); + code->CMP(8, R(RBX), Imm8(0)); + cc = CC_E; + break; + case Arm::Cond::MI: //n + NFlag(RCX); + code->CMP(8, R(RCX), Imm8(0)); + cc = CC_NE; + break; + case Arm::Cond::PL: //!n + NFlag(RCX); + code->CMP(8, R(RCX), Imm8(0)); + cc = CC_E; + break; + case Arm::Cond::VS: //v + VFlag(RDX); + code->CMP(8, R(RDX), Imm8(0)); + cc = CC_NE; + break; + case Arm::Cond::VC: //!v + VFlag(RDX); + code->CMP(8, R(RDX), Imm8(0)); + cc = CC_E; + break; + case Arm::Cond::HI: { //c & !z + const X64Reg tmp = RSI; + ZFlag(RAX); + code->MOVZX(64, 8, tmp, R(RAX)); + CFlag(RBX); + code->CMP(8, R(RBX), R(tmp)); + cc = CC_A; + break; + } + case Arm::Cond::LS: { //!c | z + const X64Reg tmp = RSI; + ZFlag(RAX); + code->MOVZX(64, 8, tmp, R(RAX)); + CFlag(RBX); + code->CMP(8, R(RBX), R(tmp)); + cc = CC_BE; + break; + } + case Arm::Cond::GE: { // n == v + const X64Reg tmp = RSI; + VFlag(RDX); + code->MOVZX(64, 8, tmp, R(RDX)); + NFlag(RCX); + code->CMP(8, R(RCX), R(tmp)); + cc = CC_E; + break; + } + case Arm::Cond::LT: { // n != v + const X64Reg tmp = RSI; + VFlag(RDX); + code->MOVZX(64, 8, tmp, R(RDX)); + NFlag(RCX); + code->CMP(8, R(RCX), R(tmp)); + cc = CC_NE; + break; + } + case Arm::Cond::GT: { // !z & (n == v) + const X64Reg tmp = RSI; + NFlag(RCX); + code->MOVZX(64, 8, tmp, R(RCX)); + VFlag(RDX); + code->XOR(8, R(tmp), R(RDX)); + ZFlag(RAX); + code->OR(8, R(tmp), R(RAX)); + code->TEST(8, R(tmp), R(tmp)); + cc = CC_Z; + break; + } + case Arm::Cond::LE: { // z | (n != v) + X64Reg tmp = RSI; + NFlag(RCX); + code->MOVZX(64, 8, tmp, R(RCX)); + VFlag(RDX); + code->XOR(8, R(tmp), R(RDX)); + ZFlag(RAX); + code->OR(8, R(tmp), R(RAX)); + code->TEST(8, R(tmp), R(tmp)); + cc = CC_NZ; + break; + } + default: + ASSERT_MSG(0, "Unknown cond %zu", static_cast(cond)); + break; } return cc; diff --git a/src/backend_x64/reg_alloc.cpp b/src/backend_x64/reg_alloc.cpp index 3fba0266..583cf174 100644 --- a/src/backend_x64/reg_alloc.cpp +++ b/src/backend_x64/reg_alloc.cpp @@ -16,17 +16,17 @@ namespace BackendX64 { static Gen::OpArg ImmediateToOpArg(const IR::Value& imm) { switch (imm.GetType()) { - case IR::Type::U1: - return Gen::Imm32(imm.GetU1()); - break; - case IR::Type::U8: - return Gen::Imm32(imm.GetU8()); - break; - case IR::Type::U32: - return Gen::Imm32(imm.GetU32()); - break; - default: - ASSERT_MSG(false, "This should never happen."); + case IR::Type::U1: + return Gen::Imm32(imm.GetU1()); + break; + case IR::Type::U8: + return Gen::Imm32(imm.GetU8()); + break; + case IR::Type::U32: + return Gen::Imm32(imm.GetU32()); + break; + default: + ASSERT_MSG(false, "This should never happen."); } } diff --git a/src/frontend/disassembler/disassembler_arm.cpp b/src/frontend/disassembler/disassembler_arm.cpp index 06fa97a9..41111a8c 100644 --- a/src/frontend/disassembler/disassembler_arm.cpp +++ b/src/frontend/disassembler/disassembler_arm.cpp @@ -35,18 +35,18 @@ public: std::string ShiftStr(ShiftType shift, Imm5 imm5) { switch (shift) { - case ShiftType::LSL: - if (imm5 == 0) return ""; - return Common::StringFromFormat(", lsl #%hhu", imm5); - case ShiftType::LSR: - if (imm5 == 0) return ", lsr #32"; - return Common::StringFromFormat(", lsr #%hhu", imm5); - case ShiftType::ASR: - if (imm5 == 0) return ", asr #32"; - return Common::StringFromFormat(", asr #%hhu", imm5); - case ShiftType::ROR: - if (imm5 == 0) return ", rrx"; - return Common::StringFromFormat(", ror #%hhu", imm5); + case ShiftType::LSL: + if (imm5 == 0) return ""; + return Common::StringFromFormat(", lsl #%hhu", imm5); + case ShiftType::LSR: + if (imm5 == 0) return ", lsr #32"; + return Common::StringFromFormat(", lsr #%hhu", imm5); + case ShiftType::ASR: + if (imm5 == 0) return ", asr #32"; + return Common::StringFromFormat(", asr #%hhu", imm5); + case ShiftType::ROR: + if (imm5 == 0) return ", rrx"; + return Common::StringFromFormat(", ror #%hhu", imm5); } ASSERT(false); return ""; @@ -54,14 +54,14 @@ public: std::string RsrStr(Reg s, ShiftType shift, Reg m) { switch (shift){ - case ShiftType::LSL: - return Common::StringFromFormat("%s, lsl %s", RegToString(m), RegToString(s)); - case ShiftType::LSR: - return Common::StringFromFormat("%s, lsr %s", RegToString(m), RegToString(s)); - case ShiftType::ASR: - return Common::StringFromFormat("%s, asr %s", RegToString(m), RegToString(s)); - case ShiftType::ROR: - return Common::StringFromFormat("%s, ror %s", RegToString(m), RegToString(s)); + case ShiftType::LSL: + return Common::StringFromFormat("%s, lsl %s", RegToString(m), RegToString(s)); + case ShiftType::LSR: + return Common::StringFromFormat("%s, lsr %s", RegToString(m), RegToString(s)); + case ShiftType::ASR: + return Common::StringFromFormat("%s, asr %s", RegToString(m), RegToString(s)); + case ShiftType::ROR: + return Common::StringFromFormat("%s, ror %s", RegToString(m), RegToString(s)); } ASSERT(false); return ""; @@ -69,14 +69,14 @@ public: std::string RorStr(Reg m, SignExtendRotation rotate) { switch (rotate) { - case SignExtendRotation::ROR_0: - return RegToString(m); - case SignExtendRotation::ROR_8: - return Common::StringFromFormat("%s, ror #8", RegToString(m)); - case SignExtendRotation::ROR_16: - return Common::StringFromFormat("%s, ror #16", RegToString(m)); - case SignExtendRotation::ROR_24: - return Common::StringFromFormat("%s, ror #24", RegToString(m)); + case SignExtendRotation::ROR_0: + return RegToString(m); + case SignExtendRotation::ROR_8: + return Common::StringFromFormat("%s, ror #8", RegToString(m)); + case SignExtendRotation::ROR_16: + return Common::StringFromFormat("%s, ror #16", RegToString(m)); + case SignExtendRotation::ROR_24: + return Common::StringFromFormat("%s, ror #24", RegToString(m)); } ASSERT(false); return ""; diff --git a/src/frontend/ir/basic_block.cpp b/src/frontend/ir/basic_block.cpp index 2863f5cd..23a07bce 100644 --- a/src/frontend/ir/basic_block.cpp +++ b/src/frontend/ir/basic_block.cpp @@ -42,18 +42,18 @@ std::string DumpBlock(const IR::Block& block) { return Common::StringFromFormat("%%%zu", inst_to_index.at(arg.GetInst())); } switch (arg.GetType()) { - case Type::U1: - return Common::StringFromFormat("#%s", arg.GetU1() ? "1" : "0"); - case Type::U8: - return Common::StringFromFormat("#%u", arg.GetU8()); - case Type::U32: - return Common::StringFromFormat("#%#x", arg.GetU32()); - case Type::RegRef: - return Arm::RegToString(arg.GetRegRef()); - case Type::ExtRegRef: - return Arm::ExtRegToString(arg.GetExtRegRef()); - default: - return ""; + case Type::U1: + return Common::StringFromFormat("#%s", arg.GetU1() ? "1" : "0"); + case Type::U8: + return Common::StringFromFormat("#%u", arg.GetU8()); + case Type::U32: + return Common::StringFromFormat("#%#x", arg.GetU32()); + case Type::RegRef: + return Arm::RegToString(arg.GetRegRef()); + case Type::ExtRegRef: + return Arm::ExtRegToString(arg.GetExtRegRef()); + default: + return ""; } }; diff --git a/src/frontend/ir/microinstruction.cpp b/src/frontend/ir/microinstruction.cpp index bb764eaf..04c1f54e 100644 --- a/src/frontend/ir/microinstruction.cpp +++ b/src/frontend/ir/microinstruction.cpp @@ -259,14 +259,14 @@ void Inst::Use(Value& value) { value.GetInst()->use_count++; switch (op){ - case Opcode::GetCarryFromOp: - value.GetInst()->carry_inst = this; - break; - case Opcode::GetOverflowFromOp: - value.GetInst()->overflow_inst = this; - break; - default: - break; + case Opcode::GetCarryFromOp: + value.GetInst()->carry_inst = this; + break; + case Opcode::GetOverflowFromOp: + value.GetInst()->overflow_inst = this; + break; + default: + break; } } @@ -274,14 +274,14 @@ void Inst::UndoUse(Value& value) { value.GetInst()->use_count--; switch (op){ - case Opcode::GetCarryFromOp: - value.GetInst()->carry_inst = nullptr; - break; - case Opcode::GetOverflowFromOp: - value.GetInst()->overflow_inst = nullptr; - break; - default: - break; + case Opcode::GetCarryFromOp: + value.GetInst()->carry_inst = nullptr; + break; + case Opcode::GetOverflowFromOp: + value.GetInst()->overflow_inst = nullptr; + break; + default: + break; } } diff --git a/src/frontend/translate/translate_arm.cpp b/src/frontend/translate/translate_arm.cpp index a218ca35..fc8facf4 100644 --- a/src/frontend/translate/translate_arm.cpp +++ b/src/frontend/translate/translate_arm.cpp @@ -99,19 +99,19 @@ bool ArmTranslatorVisitor::LinkToNextInstruction() { IREmitter::ResultAndCarry ArmTranslatorVisitor::EmitImmShift(IR::Value value, ShiftType type, Imm5 imm5, IR::Value carry_in) { switch (type) { - case ShiftType::LSL: - return ir.LogicalShiftLeft(value, ir.Imm8(imm5), carry_in); - case ShiftType::LSR: - imm5 = imm5 ? imm5 : 32; - return ir.LogicalShiftRight(value, ir.Imm8(imm5), carry_in); - case ShiftType::ASR: - imm5 = imm5 ? imm5 : 32; - return ir.ArithmeticShiftRight(value, ir.Imm8(imm5), carry_in); - case ShiftType::ROR: - if (imm5) - return ir.RotateRight(value, ir.Imm8(imm5), carry_in); - else - return ir.RotateRightExtended(value, carry_in); + case ShiftType::LSL: + return ir.LogicalShiftLeft(value, ir.Imm8(imm5), carry_in); + case ShiftType::LSR: + imm5 = imm5 ? imm5 : 32; + return ir.LogicalShiftRight(value, ir.Imm8(imm5), carry_in); + case ShiftType::ASR: + imm5 = imm5 ? imm5 : 32; + return ir.ArithmeticShiftRight(value, ir.Imm8(imm5), carry_in); + case ShiftType::ROR: + if (imm5) + return ir.RotateRight(value, ir.Imm8(imm5), carry_in); + else + return ir.RotateRightExtended(value, carry_in); } ASSERT_MSG(false, "Unreachable"); return {}; @@ -119,14 +119,14 @@ IREmitter::ResultAndCarry ArmTranslatorVisitor::EmitImmShift(IR::Value value, Sh IREmitter::ResultAndCarry ArmTranslatorVisitor::EmitRegShift(IR::Value value, ShiftType type, IR::Value amount, IR::Value carry_in) { switch (type) { - case ShiftType::LSL: - return ir.LogicalShiftLeft(value, amount, carry_in); - case ShiftType::LSR: - return ir.LogicalShiftRight(value, amount, carry_in); - case ShiftType::ASR: - return ir.ArithmeticShiftRight(value, amount, carry_in); - case ShiftType::ROR: - return ir.RotateRight(value, amount, carry_in); + case ShiftType::LSL: + return ir.LogicalShiftLeft(value, amount, carry_in); + case ShiftType::LSR: + return ir.LogicalShiftRight(value, amount, carry_in); + case ShiftType::ASR: + return ir.ArithmeticShiftRight(value, amount, carry_in); + case ShiftType::ROR: + return ir.RotateRight(value, amount, carry_in); } ASSERT_MSG(false, "Unreachable"); return {}; diff --git a/src/frontend/translate/translate_arm/extension.cpp b/src/frontend/translate/translate_arm/extension.cpp index 552c0111..9986d616 100644 --- a/src/frontend/translate/translate_arm/extension.cpp +++ b/src/frontend/translate/translate_arm/extension.cpp @@ -12,17 +12,17 @@ namespace Arm { IR::Value ArmTranslatorVisitor::SignZeroExtendRor(Reg m, SignExtendRotation rotate) { IR::Value rotated, reg_m = ir.GetRegister(m); switch (rotate) { - case SignExtendRotation::ROR_0: - rotated = reg_m; - break; - case SignExtendRotation::ROR_8: - rotated = ir.RotateRight(reg_m, ir.Imm8(8), ir.Imm1(0)).result; - break; - case SignExtendRotation::ROR_16: - rotated = ir.RotateRight(reg_m, ir.Imm8(16), ir.Imm1(0)).result; - break; - case SignExtendRotation::ROR_24: - rotated = ir.RotateRight(reg_m, ir.Imm8(24), ir.Imm1(0)).result; + case SignExtendRotation::ROR_0: + rotated = reg_m; + break; + case SignExtendRotation::ROR_8: + rotated = ir.RotateRight(reg_m, ir.Imm8(8), ir.Imm1(0)).result; + break; + case SignExtendRotation::ROR_16: + rotated = ir.RotateRight(reg_m, ir.Imm8(16), ir.Imm1(0)).result; + break; + case SignExtendRotation::ROR_24: + rotated = ir.RotateRight(reg_m, ir.Imm8(24), ir.Imm1(0)).result; } return rotated; } diff --git a/src/frontend/translate/translate_arm/load_store.cpp b/src/frontend/translate/translate_arm/load_store.cpp index 75aa220b..26299cd5 100644 --- a/src/frontend/translate/translate_arm/load_store.cpp +++ b/src/frontend/translate/translate_arm/load_store.cpp @@ -217,14 +217,14 @@ bool ArmTranslatorVisitor::arm_LDRD_lit(Cond cond, bool U, Reg t, Imm4 imm8a, Im auto data_b = ir.ReadMemory32(address_b); switch (t) { - case Reg::PC: - data_a = ir.Add(data_a, ir.Imm32(4)); - break; - case Reg::LR: - data_b = ir.Add(data_b, ir.Imm32(4)); - break; - default: - break; + case Reg::PC: + data_a = ir.Add(data_a, ir.Imm32(4)); + break; + case Reg::LR: + data_b = ir.Add(data_b, ir.Imm32(4)); + break; + default: + break; } if (t == Reg::PC) { diff --git a/src/ir_opt/dead_code_elimination_pass.cpp b/src/ir_opt/dead_code_elimination_pass.cpp index d6e5801a..592195a9 100644 --- a/src/ir_opt/dead_code_elimination_pass.cpp +++ b/src/ir_opt/dead_code_elimination_pass.cpp @@ -15,46 +15,47 @@ namespace Optimization { void DeadCodeElimination(IR::Block& block) { const auto is_side_effect_free = [](IR::Opcode op) -> bool { switch (op) { - case IR::Opcode::Breakpoint: - case IR::Opcode::SetRegister: - case IR::Opcode::SetExtendedRegister32: - case IR::Opcode::SetExtendedRegister64: - case IR::Opcode::SetNFlag: - case IR::Opcode::SetZFlag: - case IR::Opcode::SetCFlag: - case IR::Opcode::SetVFlag: - case IR::Opcode::OrQFlag: - case IR::Opcode::BXWritePC: - case IR::Opcode::CallSupervisor: - case IR::Opcode::PushRSB: - case IR::Opcode::FPAbs32: - case IR::Opcode::FPAbs64: - case IR::Opcode::FPAdd32: - case IR::Opcode::FPAdd64: - case IR::Opcode::FPDiv32: - case IR::Opcode::FPDiv64: - case IR::Opcode::FPMul32: - case IR::Opcode::FPMul64: - case IR::Opcode::FPNeg32: - case IR::Opcode::FPNeg64: - case IR::Opcode::FPSqrt32: - case IR::Opcode::FPSqrt64: - case IR::Opcode::FPSub32: - case IR::Opcode::FPSub64: - case IR::Opcode::ClearExclusive: - case IR::Opcode::SetExclusive: - case IR::Opcode::WriteMemory8: - case IR::Opcode::WriteMemory16: - case IR::Opcode::WriteMemory32: - case IR::Opcode::WriteMemory64: - case IR::Opcode::ExclusiveWriteMemory8: - case IR::Opcode::ExclusiveWriteMemory16: - case IR::Opcode::ExclusiveWriteMemory32: - case IR::Opcode::ExclusiveWriteMemory64: - return false; - default: - ASSERT(IR::GetTypeOf(op) != IR::Type::Void); - return true; + case IR::Opcode::Breakpoint: + case IR::Opcode::SetRegister: + case IR::Opcode::SetExtendedRegister32: + case IR::Opcode::SetExtendedRegister64: + case IR::Opcode::SetCpsr: + case IR::Opcode::SetNFlag: + case IR::Opcode::SetZFlag: + case IR::Opcode::SetCFlag: + case IR::Opcode::SetVFlag: + case IR::Opcode::OrQFlag: + case IR::Opcode::BXWritePC: + case IR::Opcode::CallSupervisor: + case IR::Opcode::PushRSB: + case IR::Opcode::FPAbs32: + case IR::Opcode::FPAbs64: + case IR::Opcode::FPAdd32: + case IR::Opcode::FPAdd64: + case IR::Opcode::FPDiv32: + case IR::Opcode::FPDiv64: + case IR::Opcode::FPMul32: + case IR::Opcode::FPMul64: + case IR::Opcode::FPNeg32: + case IR::Opcode::FPNeg64: + case IR::Opcode::FPSqrt32: + case IR::Opcode::FPSqrt64: + case IR::Opcode::FPSub32: + case IR::Opcode::FPSub64: + case IR::Opcode::ClearExclusive: + case IR::Opcode::SetExclusive: + case IR::Opcode::WriteMemory8: + case IR::Opcode::WriteMemory16: + case IR::Opcode::WriteMemory32: + case IR::Opcode::WriteMemory64: + case IR::Opcode::ExclusiveWriteMemory8: + case IR::Opcode::ExclusiveWriteMemory16: + case IR::Opcode::ExclusiveWriteMemory32: + case IR::Opcode::ExclusiveWriteMemory64: + return false; + default: + ASSERT(IR::GetTypeOf(op) != IR::Type::Void); + return true; } }; diff --git a/src/ir_opt/get_set_elimination_pass.cpp b/src/ir_opt/get_set_elimination_pass.cpp index a1155dee..8db394a8 100644 --- a/src/ir_opt/get_set_elimination_pass.cpp +++ b/src/ir_opt/get_set_elimination_pass.cpp @@ -49,63 +49,63 @@ void GetSetElimination(IR::Block& block) { for (auto inst = block.begin(); inst != block.end(); ++inst) { switch (inst->GetOpcode()) { - case IR::Opcode::SetRegister: { - Arm::Reg reg = inst->GetArg(0).GetRegRef(); - if (reg == Arm::Reg::PC) - break; - size_t reg_index = static_cast(reg); - do_set(reg_info[reg_index], inst->GetArg(1), inst); - break; - } - case IR::Opcode::GetRegister: { - Arm::Reg reg = inst->GetArg(0).GetRegRef(); - ASSERT(reg != Arm::Reg::PC); - size_t reg_index = static_cast(reg); - do_get(reg_info[reg_index], inst); - break; - } - case IR::Opcode::SetNFlag: { - do_set(n_info, inst->GetArg(0), inst); - break; - } - case IR::Opcode::GetNFlag: { - do_get(n_info, inst); - break; - } - case IR::Opcode::SetZFlag: { - do_set(z_info, inst->GetArg(0), inst); - break; - } - case IR::Opcode::GetZFlag: { - do_get(z_info, inst); - break; - } - case IR::Opcode::SetCFlag: { - do_set(c_info, inst->GetArg(0), inst); - break; - } - case IR::Opcode::GetCFlag: { - do_get(c_info, inst); - break; - } - case IR::Opcode::SetVFlag: { - do_set(v_info, inst->GetArg(0), inst); - break; - } - case IR::Opcode::GetVFlag: { - do_get(v_info, inst); - break; - } - case IR::Opcode::SetCpsr: - case IR::Opcode::GetCpsr: { - n_info = {}; - z_info = {}; - c_info = {}; - v_info = {}; - break; - } - default: + case IR::Opcode::SetRegister: { + Arm::Reg reg = inst->GetArg(0).GetRegRef(); + if (reg == Arm::Reg::PC) break; + size_t reg_index = static_cast(reg); + do_set(reg_info[reg_index], inst->GetArg(1), inst); + break; + } + case IR::Opcode::GetRegister: { + Arm::Reg reg = inst->GetArg(0).GetRegRef(); + ASSERT(reg != Arm::Reg::PC); + size_t reg_index = static_cast(reg); + do_get(reg_info[reg_index], inst); + break; + } + case IR::Opcode::SetNFlag: { + do_set(n_info, inst->GetArg(0), inst); + break; + } + case IR::Opcode::GetNFlag: { + do_get(n_info, inst); + break; + } + case IR::Opcode::SetZFlag: { + do_set(z_info, inst->GetArg(0), inst); + break; + } + case IR::Opcode::GetZFlag: { + do_get(z_info, inst); + break; + } + case IR::Opcode::SetCFlag: { + do_set(c_info, inst->GetArg(0), inst); + break; + } + case IR::Opcode::GetCFlag: { + do_get(c_info, inst); + break; + } + case IR::Opcode::SetVFlag: { + do_set(v_info, inst->GetArg(0), inst); + break; + } + case IR::Opcode::GetVFlag: { + do_get(v_info, inst); + break; + } + case IR::Opcode::SetCpsr: + case IR::Opcode::GetCpsr: { + n_info = {}; + z_info = {}; + c_info = {}; + v_info = {}; + break; + } + default: + break; } } } diff --git a/tests/arm/fuzz_arm.cpp b/tests/arm/fuzz_arm.cpp index 23283d97..7f8a7246 100644 --- a/tests/arm/fuzz_arm.cpp +++ b/tests/arm/fuzz_arm.cpp @@ -142,16 +142,16 @@ public: for (int i = 0; i < 32; i++) { const u32 bit = 1u << (31 - i); switch (format[i]) { - case '0': - mask |= bit; - break; - case '1': - bits |= bit; - mask |= bit; - break; - default: - // Do nothing - break; + case '0': + mask |= bit; + break; + case '1': + bits |= bit; + mask |= bit; + break; + default: + // Do nothing + break; } } } @@ -514,36 +514,36 @@ TEST_CASE("Fuzz ARM data processing instructions", "[JitX64]") { u32 S = RandInt(0, 1); switch (instruction_set) { - case 0: { - InstructionGenerator instruction = imm_instructions[RandInt(0, imm_instructions.size() - 1)]; - u32 Rd = RandInt(0, Rd_can_be_r15 ? 15 : 14); - if (Rd == 15) S = false; - u32 Rn = RandInt(0, 15); - u32 shifter_operand = RandInt(0, 0xFFF); - u32 assemble_randoms = (shifter_operand << 0) | (Rd << 12) | (Rn << 16) | (S << 20) | (cond << 28); - return instruction.Bits() | (assemble_randoms & ~instruction.Mask()); - } - case 1: { - InstructionGenerator instruction = reg_instructions[RandInt(0, reg_instructions.size() - 1)]; - u32 Rd = RandInt(0, Rd_can_be_r15 ? 15 : 14); - if (Rd == 15) S = false; - u32 Rn = RandInt(0, 15); - u32 shifter_operand = RandInt(0, 0xFFF); - u32 assemble_randoms = - (shifter_operand << 0) | (Rd << 12) | (Rn << 16) | (S << 20) | (cond << 28); - return instruction.Bits() | (assemble_randoms & ~instruction.Mask()); - } - case 2: { - InstructionGenerator instruction = rsr_instructions[RandInt(0, rsr_instructions.size() - 1)]; - u32 Rd = RandInt(0, 14); // Rd can never be 15. - u32 Rn = RandInt(0, 14); - u32 Rs = RandInt(0, 14); - int rotate = RandInt(0, 3); - u32 Rm = RandInt(0, 14); - u32 assemble_randoms = - (Rm << 0) | (rotate << 5) | (Rs << 8) | (Rd << 12) | (Rn << 16) | (S << 20) | (cond << 28); - return instruction.Bits() | (assemble_randoms & ~instruction.Mask()); - } + case 0: { + InstructionGenerator instruction = imm_instructions[RandInt(0, imm_instructions.size() - 1)]; + u32 Rd = RandInt(0, Rd_can_be_r15 ? 15 : 14); + if (Rd == 15) S = false; + u32 Rn = RandInt(0, 15); + u32 shifter_operand = RandInt(0, 0xFFF); + u32 assemble_randoms = (shifter_operand << 0) | (Rd << 12) | (Rn << 16) | (S << 20) | (cond << 28); + return instruction.Bits() | (assemble_randoms & ~instruction.Mask()); + } + case 1: { + InstructionGenerator instruction = reg_instructions[RandInt(0, reg_instructions.size() - 1)]; + u32 Rd = RandInt(0, Rd_can_be_r15 ? 15 : 14); + if (Rd == 15) S = false; + u32 Rn = RandInt(0, 15); + u32 shifter_operand = RandInt(0, 0xFFF); + u32 assemble_randoms = + (shifter_operand << 0) | (Rd << 12) | (Rn << 16) | (S << 20) | (cond << 28); + return instruction.Bits() | (assemble_randoms & ~instruction.Mask()); + } + case 2: { + InstructionGenerator instruction = rsr_instructions[RandInt(0, rsr_instructions.size() - 1)]; + u32 Rd = RandInt(0, 14); // Rd can never be 15. + u32 Rn = RandInt(0, 14); + u32 Rs = RandInt(0, 14); + int rotate = RandInt(0, 3); + u32 Rm = RandInt(0, 14); + u32 assemble_randoms = + (Rm << 0) | (rotate << 5) | (Rs << 8) | (Rd << 12) | (Rn << 16) | (S << 20) | (cond << 28); + return instruction.Bits() | (assemble_randoms & ~instruction.Mask()); + } } return 0; }; diff --git a/tests/arm/fuzz_thumb.cpp b/tests/arm/fuzz_thumb.cpp index 739c9444..806a98ca 100644 --- a/tests/arm/fuzz_thumb.cpp +++ b/tests/arm/fuzz_thumb.cpp @@ -130,16 +130,16 @@ public: for (int i = 0; i < 16; i++) { const u16 bit = 1 << (15 - i); switch (format[i]) { - case '0': - mask |= bit; - break; - case '1': - bits |= bit; - mask |= bit; - break; - default: - // Do nothing - break; + case '0': + mask |= bit; + break; + case '1': + bits |= bit; + mask |= bit; + break; + default: + // Do nothing + break; } } }